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41. 发明申请

US20100052025A1 SOI MUGFETS HAVING SINGLE GATE ELECTRODE LEVEL 有权
标题翻译：具有单门电极水平的SOI MUGFETS
公开(公告)号：US20100052025A1
公开(公告)日：2010-03-04
申请号：US12199041
申请日：2008-08-27
申请人： Howard Lee Tigelaar , Cloves Rinn Cleavelin , Andrew Marshall , Weize Xiong
发明人： Howard Lee Tigelaar , Cloves Rinn Cleavelin , Andrew Marshall , Weize Xiong
IPC分类号： H01L27/115
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： A silicon on insulator (SOI) multi-gate field effect transistor electrically Programmable Read-Only Memory (MuFET EPROM) includes a substrate having a dielectric surface. A first semiconducting region is in or on the dielectric surface. A source region, a drain region and a channel region interposed between the source and drain are formed in first semiconducting region. A gate dielectric layer is on the channel region. At least a second semiconducting region in or on the dielectric surface is spaced apart from the first semiconducting region. A first electrode layer comprises a first electrode portion including a transistor gate electrode and a control gate electrode electrically isolated from one another. The transistor gate overlies the channel region to form a transistor. The control gate extends to overlay a portion of the second semiconducting region. The transistor gate and thus the transistor and the control gate are capacitively coupled to one another by at least one MOS coupling capacitor, with one plate of the MOS coupling capacitor ohmically coupled to or including the second semiconducting region.
摘要翻译：绝缘体上硅（SOI）多栅极场效应晶体管电可编程只读存储器（MuFET EPROM）包括具有电介质表面的衬底。第一半导电区域位于电介质表面中或其上。源极区域，漏极区域和介于源极和漏极之间的沟道区域形成在第一半导体区域中。栅介质层位于沟道区上。电介质表面中或电介质表面上的至少第二半导体区域与第一半导体区域间隔开。第一电极层包括第一电极部分，其包括晶体管栅电极和彼此电隔离的控制栅电极。晶体管栅极覆盖沟道区以形成晶体管。控制门延伸以覆盖第二半导体区域的一部分。晶体管栅极，因此晶体管和控制栅极通过至少一个MOS耦合电容器彼此电容耦合，MOS耦合电容的一个板欧姆耦合到或包括第二半导体区域。

42. 发明申请

US20100002494A1 Memory Device with Memory Cell Including MuGFET and FIN Capacitor 有权
标题翻译：具有包含MuGFET和FIN电容器的存储单元的存储器件
公开(公告)号：US20100002494A1
公开(公告)日：2010-01-07
申请号：US12554660
申请日：2009-09-04
申请人： Weize Xiong , Andrew Marshall , Cloves Rinn Cleavelin , Howard Lee Tigelaar
发明人： Weize Xiong , Andrew Marshall , Cloves Rinn Cleavelin , Howard Lee Tigelaar
IPC分类号： G11C11/24 , H01L27/108 , G11C7/00
CPC分类号： H01L29/94 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L28/60 , H01L29/785 , H01L29/7855
摘要： One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.
摘要翻译：本发明的一个实施例涉及一种存储单元。存储单元包括与半导体鳍片的第一区域相关联的多栅极场效应晶体管。存储单元还包括耦合到多栅极场效应晶体管的漏极并与半导体鳍片的第二区域相关联的散热片电容器，其中散热片电容器在第二区域中具有大致简并掺杂浓度。还公开了其它装置和方法。

43. 发明申请

US20090130817A1 METHOD TO ELIMINATE RE-CRYSTALLIZATION BORDER DEFECTS GENERATED DURING SOLID PHASE EPITAXY OF A DSB SUBSTRATE 有权
标题翻译：消除DSB基板固体相外延生成的再结晶边界缺陷的方法
公开(公告)号：US20090130817A1
公开(公告)日：2009-05-21
申请号：US11941187
申请日：2007-11-16
申请人： Angelo Pinto , Weize Xiong , Manfred Ramin
发明人： Angelo Pinto , Weize Xiong , Manfred Ramin
IPC分类号： H01L21/762
CPC分类号： H01L21/187 , H01L21/02532 , H01L21/02609 , H01L21/02667 , H01L21/76224
摘要： A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation, a second crystal orientation, and a border region disposed between the first and second crystal orientations. The border region further has a defect associated with an interface of the first crystal orientation and second the second crystal orientation, wherein the defect generally extends a distance into the semiconductor body from a surface of the body. A sacrificial portion of the semiconductor body is removed from the surface thereof, wherein removing the sacrificial portion at least partially removes the defect. The sacrificial portion can be defined by oxidizing the surface at low temperature, wherein the oxidation at least partially consumes the defect. The sacrificial portion can also be removed by CMP. An STI feature may be further formed over the defect after removal of the sacrificial portion, therein consuming any remaining defect.
摘要翻译：一种用于半导体处理的方法提供了具有第一晶体取向，第二晶体取向和设置在第一和第二晶体取向之间的边界区域的DSB半导体本体。边界区域还具有与第一晶体取向和第二晶体取向的界面相关联的缺陷，其中缺陷通常从身体的表面延伸到半导体本体中的距离。从其表面去除半导体本体的牺牲部分，其中去除牺牲部分至少部分地去除缺陷。牺牲部分可以通过在低温下氧化表面来限定，其中氧化至少部分地消耗缺陷。牺牲部分也可以通过CMP去除。在去除牺牲部分之后，可以在缺陷上进一步形成STI特征，其中消耗任何剩余的缺陷。

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