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    • 42. 发明申请
    • FIELD EFFECT TRANSISTOR ARRANGEMENT
    • 场效应晶体管布置
    • US20160218212A1
    • 2016-07-28
    • US14900704
    • 2014-06-25
    • TECHNISCHE UNIVERSITÄT DARMSTADT
    • Udo SCHWALKEFrank WESSELYTilmann KRAUSS
    • H01L29/78H01L29/06H01L29/40
    • H01L29/7838H01L29/0649H01L29/404H01L29/7839H01L29/78645H01L29/78648H01L29/78654
    • A field effect transistor arrangement having as planar channel layer comprises semiconductor material, the whole surface of the underside of the layer being applied to an upper side of an electrically insulating substrate layer and the upper side of the planar channel layer being covered by an insulation layer. The arrangement has a source electrode on a first side edge of the channel layer and a drain electrode on a second side edge of the channel layer and a control electrode arranged above the channel layer. An adjusting electrode is arranged on an underside of the substrate layer. A contact region between the source and drain electrodes and the planar channel layer is in each case configured as a midgap Schottky barrier. A respective barrier control electrode is arranged in the vicinity of the contact region of the source electrode and of the drain electrode, Each barrier control electrode can have a section that projects outwards in the direction of the planar channel layer.
    • 具有平面沟道层的场效应晶体管布置包括半导体材料,该层的下侧的整个表面被施加到电绝缘基底层的上侧,并且平面通道层的上侧被绝缘层覆盖 。 该布置在沟道层的第一侧边缘上具有源电极,在沟道层的第二侧边缘上具有漏电极,以及布置在沟道层上方的控制电极。 调整电极设置在基底层的下侧。 源电极和漏电极之间的接触区域和平面沟道层在每种情况下被配置为中隙肖特基势垒。 各栅极控制电极配置在源电极和漏电极的接触区域附近。每个势垒控制电极可以具有在平面沟道层的方向上向外突出的部分。