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41. 发明申请

US20130320455A1 SEMICONDUCTOR DEVICE WITH ISOLATED BODY PORTION 有权
标题翻译：具有隔离体部分的半导体器件
公开(公告)号：US20130320455A1
公开(公告)日：2013-12-05
申请号：US13995418
申请日：2011-12-20
申请人： Annalisa Cappellani , Stephen M. Cea , Tahir Ghani , Harry Gomez , Jack T. Kavalieros , Patrick H. Keys , Seiyon Kim , Kelin J. Kuhn , Aaron D. Lilak , Rafael Rios , Mayank Sahni
发明人： Annalisa Cappellani , Stephen M. Cea , Tahir Ghani , Harry Gomez , Jack T. Kavalieros , Patrick H. Keys , Seiyon Kim , Kelin J. Kuhn , Aaron D. Lilak , Rafael Rios , Mayank Sahni
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/66818 , B82Y10/00 , H01L21/762 , H01L21/76216 , H01L27/1203 , H01L29/0649 , H01L29/0653 , H01L29/0673 , H01L29/42392 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.
摘要翻译：描述具有隔离主体部分的半导体器件。例如，半导体结构包括设置在半导体衬底之上的半导体本体。半导体主体包括沟道区和沟道区两侧的一对源极和漏极区。隔离基座设置在半导体本体和半导体衬底之间。栅极电极堆叠至少部分地围绕半导体主体的沟道区域的一部分。

42. 发明申请

US20130161756A1 NANOWIRE TRANSISTOR DEVICES AND FORMING TECHNIQUES 有权
公开(公告)号：US20130161756A1
公开(公告)日：2013-06-27
申请号：US13560531
申请日：2012-07-27
申请人： Glenn A. Glass , Kelin J. Kuhn , Seiyon Kim , Anand S. Murthy , Daniel B. Aubertine
发明人： Glenn A. Glass , Kelin J. Kuhn , Seiyon Kim , Anand S. Murthy , Daniel B. Aubertine
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/0676 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/7855 , H01L29/78696
摘要： Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

43. 发明授权

US07560358B1 Method of preparing active silicon regions for CMOS or other devices 有权
标题翻译：为CMOS或其他器件制备活性硅区域的方法
公开(公告)号：US07560358B1
公开(公告)日：2009-07-14
申请号：US11967708
申请日：2007-12-31
申请人： Seiyon Kim , Peter L. D. Chang , Ibrahim Ban , Willy Rachmady
发明人： Seiyon Kim , Peter L. D. Chang , Ibrahim Ban , Willy Rachmady
IPC分类号： H01L27/01
CPC分类号： H01L21/823878 , H01L21/823828 , H01L21/84 , H01L27/1203 , H01L29/78648
摘要： A method of preparing active silicon regions for CMOS or other devices includes providing a structure including a silicon substrate (210, 410) having formed thereon first and second silicon diffusion lines (110, 420), both of which include first and second silicon layers (211, 213, 421, 423), a silicon germanium layer (212, 422), and a mask layer (214, 424). The method further includes forming an oxide layer (430) in first and second regions of the structure, forming a polysilicon layer (510) over the oxide layer, removing the polysilicon layer from the first region and depositing oxide (610) therein in order to form an oxide anchor, removing the polysilicon layer from the second region, removing the silicon germanium layer, filling the first and second gaps with an electrically insulating material (910), and depositing oxide in the second region.
摘要翻译：制备用于CMOS或其它器件的活性硅区域的方法包括提供包括在其上形成有第一和第二硅扩散线（110,420）的硅衬底（210,410）的结构，它们都包括第一和第二硅层（ 211,213,421,423），硅锗层（212,422）和掩模层（214,424）。所述方法还包括在所述结构的第一和第二区域中形成氧化物层（430），在所述氧化物层上形成多晶硅层（510），从所述第一区域去除多晶硅层并在其中沉积氧化物（610），以便形成氧化物锚，从第二区域去除多晶硅层，去除硅锗层，用电绝缘材料（910）填充第一和第二间隙，以及在第二区域中沉积氧化物。

44. 发明申请

US20080023726A1 Schottky gate metallization for semiconductor devices 审中-公开
标题翻译：用于半导体器件的肖特基栅极金属化
公开(公告)号：US20080023726A1
公开(公告)日：2008-01-31
申请号：US11805855
申请日：2007-05-24
申请人： Ilesanmi Adesida , Seiyon Kim , Liang Wang
发明人： Ilesanmi Adesida , Seiyon Kim , Liang Wang
IPC分类号： H01L29/739 , H01L21/28 , H01L29/80 , H01L21/338
CPC分类号： H01L29/7784 , H01L21/8252 , H01L27/0605 , H01L27/0883 , H01L27/095 , H01L29/475 , H01L29/872
摘要： A method of forming a Schottky barrier contact to a semiconductor material, includes the following steps: depositing an iridium contact on a surface of the semiconductor material; and annealing the iridium contact to form a Schottky barrier contact to the semiconductor material. For an example of an iridium Schottky contact on an InAlAs semiconductor material, the annealing temperature is preferably in the range about 350° C. to 500° C.
摘要翻译：形成与半导体材料的肖特基势垒接触的方法包括以下步骤：在半导体材料的表面上沉积铱触点; 以及对所述铱接触进行退火以与所述半导体材料形成肖特基势垒接触。对于InAlAs半导体材料上的铱肖特基接触的实例，退火温度优选在约350℃至500℃的范围内。

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