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41. 发明授权

US06584595B2 Technique for correcting single-bit errors in caches with sub-block parity bits 有权
公开(公告)号：US06584595B2
公开(公告)日：2003-06-24
申请号：US09975225
申请日：2001-10-11
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： G11C2900
CPC分类号： G06F11/1064 , G06F11/1012
摘要： A data block includes a plurality of sub-blocks. Each sub-block includes a sub-block check bit that may be used to detect the presence of a bit error within the sub-block. A composite sub-block is generated, which is the column-wise exclusive-or of the bits of each sub-block. In one embodiment, the composite sub-block is not stored, but rather used for computational purposes only. A plurality of composite check bits is used to detect a bit position of a bit error within the composite sub-block. If a bit error within the data block occurs, the sub-block check bits may be used to detect in which sub-block the error occurred. The composite check bits may be used to determine which bit position of the composite sub-block is erroneous. The erroneous bit position of the composite sub-block also identifies the bit position of the erroneous bit in the sub-block identified by the sub-block check bits. Accordingly, the sub-block and the bit position within the sub-block may be detected by using the sub-block check bits and the composite check bits.

42. 发明授权

US06473880B1 System and method for protecting data and correcting bit errors due to component failures 有权
标题翻译：用于保护数据和纠正由于组件故障导致的位错误的系统和方法
公开(公告)号：US06473880B1
公开(公告)日：2002-10-29
申请号：US09323795
申请日：1999-06-01
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： G06F1100
CPC分类号： G06F11/1028
摘要： A system for protecting data and correcting bit errors due to component failures includes a check bits generation unit which receives and encodes data to be protected. The check bits generation unit effectively partitions the data into a plurality of logical groups. The check bits generation unit generates a parity bit for each of the logical groups, and additionally generates a global error correction. The global error correction code is equivalent to the result of generating individual error correction codes for each logical group and combining them in a predetermined manner. An error correction unit is coupled to receive the plurality of data bits and the check bits following storage or transmission. A global syndrome code is generated such that, with knowledge of the specific logical groups that have a single bit error, a value indicative of the location of the error in such groups may be derived from the global syndrome code.
摘要翻译：用于保护数据和由于组件故障而校正位错误的系统包括接收并编码要保护的数据的校验位生成单元。校验位生成单元有效地将数据分割成多个逻辑组。校验位生成单元为每个逻辑组生成奇偶校验位，并且还生成全局误差校正。全局纠错码等效于为每个逻辑组产生各个纠错码并以预定的方式组合它们的结果。耦合差错纠正单元以在存储或传输之后接收多个数据位和校验位。生成全局校正码，使得通过具有单个位错误的特定逻辑组的知识，可以从全局校正子码导出指示这些组中的错误的位置的值。

43. 发明授权

US06301680B1 Technique for correcting single-bit errors and detecting paired double-bit errors 有权
标题翻译：纠正单位错误和检测配对双位错误的技术
公开(公告)号：US06301680B1
公开(公告)日：2001-10-09
申请号：US09160215
申请日：1998-09-24
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： G06F1100
CPC分类号： H03M13/19
摘要： A technique to detect and correct single bit errors and to detect paired bit errors in a data block. Two bits of the data block are paired and transferred on the same data path in different cycles. Check bits are computed prior to transferring the data block. A syndrome bits vector is computed when the data block is received. The syndrome bits vector includes a number of syndrome bits that is identical to the number of check bits. A value of the syndrome bits vector is used to detect and correct single bit errors and to detect paired double bit errors that occur in the data block without using an extended check bit. If the syndrome bits vector contains all zero bits, the data block is accepted without modification. If the syndrome bits vector is identical to a predetermined special vector V, a paired double bit error has occurred and either an unrecoverable error message is generated or a re-operation on the data block is requested. If the syndrome bits vector is not identical to V but contains bits that correspond to one of a plurality of assignment vectors, a single bit error is detected and corrected. Each of the assignment vectors corresponds to one of the bits in the data block and indicates what syndrome bits the corresponding bit in the data block is contributing to.
摘要翻译：一种检测和纠正单个位错误并检测数据块中的配对位错误的技术。数据块的两位被配对并在不同周期的相同数据路径上传输。在传输数据块之前计算校验位。当接收到数据块时，计算校正子位向量。校正子位向量包括与校验位数相同的多个校正子位。校正子位向量的值用于检测和纠正单个位错误，并检测数据块中发生的配对双位错误，而不使用扩展检查位。如果校正子位向量包含全部零位，则数据块被接受而无需修改。如果校正子比特向量与预定的特殊向量V相同，则发生配对双位错误，并且产生不可恢复的错误消息或者请求对数据块进行重新操作。如果校正子位向量与V不相同，但包含与多个赋值向量中的一个对应的位，则检测并校正单个位错误。每个分配向量对应于数据块中的一个比特，并且指示数据块中的相应比特对哪个校正子比特有贡献。

44. 发明授权

US06233716B1 Technique for partitioning data to correct memory part failures 有权
标题翻译：分割数据以纠正内存部分故障的技术
公开(公告)号：US06233716B1
公开(公告)日：2001-05-15
申请号：US09160770
申请日：1998-09-24
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： G11C2900
CPC分类号： G06F11/1028
摘要： The bits of a data block are assigned to a plurality of logical groups such that at most one bit corresponding to a component is assigned to a logical group. This assignment ensures that a component failure may introduce at most one bit error to a logical group. A number of bits in a logical group is selected to reduce the number of check bits for a given number of data bits. Error correction may be performed within each logical group to correct single errors within the logical group. Because each logical group is assigned at most one bit corresponding to a component, component failures may be detected and corrected.
摘要翻译：将数据块的比特分配给多个逻辑组，使得至多一个对应于分量的比特被分配给逻辑组。此分配确保组件故障最多可能向逻辑组引入一个位错误。选择逻辑组中的位数以减少给定数量的数据位的校验位的数量。可以在每个逻辑组内执行纠错，以纠正逻辑组中的单个错误。由于每个逻辑组最多分配一个与组件相对应的位，所以可以检测和校正组件故障。

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