专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明专利

JP2012085357A Communication system and method over local area network wiring 有权
标题翻译：通信系统和方法在本地区域网络接线
公开(公告)号：JP2012085357A
公开(公告)日：2012-04-26
申请号：JP2012005985
申请日：2012-01-16
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： BINDER YEHUDA
IPC分类号： H04J99/00 , H04M11/00 , H04L5/20 , H04L12/64 , H04L12/66 , H04M20060101 , H04M3/00 , H04M11/06
CPC分类号： H04L5/20 , H04B3/542 , H04L12/66 , H04L2012/6421 , H04L2012/6424 , H04L2012/644 , H04M11/062 , H04M11/066 , Y10S439/95 , Y10T307/297
摘要： PROBLEM TO BE SOLVED: To provide a method and apparatus for enabling a local area network wiring structure to simultaneously carry digital data and analog telephone signals on the same transmission medium.SOLUTION: The method and apparatus is particularly applicable to a network in star topology, in which remote data units (e.g. personal computers) are each connected to a hub through a cable comprising at least two pairs of conductors, providing a data communication path in each direction. Modules at each end of the cable provide a phantom path for telephony (voice band) signals between a telephone near the data set and a PBX, through both conductor pairs in a phantom circuit arrangement. All such communication paths function simultaneously and without mutual interference. The modules comprise simple and inexpensive passive circuit components.
摘要翻译：要解决的问题：提供一种使局域网布线结构能够在相同传输介质上同时携带数字数据和模拟电话信号的方法和装置。解决方案：该方法和装置特别适用于星形拓扑网络，其中远程数据单元（例如个人计算机）通过包括至少两对导体的电缆连接到集线器，提供数据通信每个方向的路径。电缆每端的模块通过虚拟电路布置的两个导线对提供了数据集附近的电话和PBX之间的电话（语音频带）信号的幻像路径。所有这些通信路径同时工作，没有相互干扰。这些模块包括简单而廉价的无源电路组件。版权所有（C）2012，JPO＆INPIT

42. 发明专利

JP2012085318A Clock regeneration and timing method in system having memory controller using a plurality of devices and flexible data arrangement 有权
标题翻译：使用多种设备和灵活数据安排的存储控制器系统中的时钟再生和时序方法
公开(公告)号：JP2012085318A
公开(公告)日：2012-04-26
申请号：JP2011251459
申请日：2011-11-17
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： PYEON HONG BEOM , GILLINGHAM PETER
IPC分类号： H04L7/02 , G06F1/06 , G06F1/08
CPC分类号： G06F1/10 , G11C5/025 , G11C7/02 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C7/20 , G11C7/22 , G11C7/222 , H01L25/0657 , H01L2224/32145 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H04L7/0008 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a system having a main controller and a plurality of semiconductor devices connected in series, where each device stores data, and the controller supplies a clock for synchronizing operation of the devices.SOLUTION: Each device has a PLL which is enabled or disabled selectively by an enable signal. The PLL of a selected device is enabled by an enable signal and other devices are disabled. An enabled PLL supplies a plurality of reproduction clocks with phase shift equal to a multiple of 90°. Data transfer is synchronized with one of reproduced clocks. In the device of a disabled PLL, data transfer is synchronized with an input clock. By the enabled and disabled PLL, each device performs source synchronization clocking and common synchronization clocking. Lowermost bit of the device identifier of the last device determines clock arrangement.
摘要翻译：要解决的问题：为了提供一种具有主控制器和串联连接的多个半导体器件的系统，其中每个器件存储数据，并且控制器提供用于器件的同步操作的时钟。解决方案：每个器件都具有通过使能信号有选择地使能或禁止的PLL。所选器件的PLL由使能信号使能，其他器件被禁止。使能的PLL提供多个等于90°的倍数的相移的再现时钟。数据传输与再生时钟之一同步。在禁用PLL的器件中，数据传输与输入时钟同步。通过使能和禁用的PLL，每个器件执行源同步时钟和公共同步时钟。最后一个设备的设备标识符的最低位确定时钟布置。版权所有（C）2012，JPO＆INPIT

43. 发明专利

JP2011054204A System and method for operating memory devices of mixed type 有权
标题翻译：用于操作混合类型的存储器件的系统和方法
公开(公告)号：JP2011054204A
公开(公告)日：2011-03-17
申请号：JP2010257825
申请日：2010-11-18
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： OH HAK JUNE , PYEON HONG BEOM , KIM JIN-KI
IPC分类号： G06F12/06 , G06F12/04 , G06F13/16
CPC分类号： G11C16/08 , G11C7/10 , G11C7/1078 , G11C7/20
摘要： PROBLEM TO BE SOLVED: To provide a memory system wherein a memory controller controls memory devices inside a serial interconnection configuration. SOLUTION: The memory controller includes: an output port for sending memory commands; and an input port for receiving memory responses related to the memory commands requesting the memory responses. Each memory device includes a memory, such as a NAND-type flash memory, a NOR-type flash memory, a RAM, and a static RAM. Each memory command is specific to a memory type of a target memory device. A data path for the memory commands and the memory responses is provided by interconnection. A given memory command traverses the memory devices to reach a desired memory device of the serial interconnection configuration. When receiving, the desired memory device executes the given memory command, and sends the memory response to the next memory device. The memory response is transferred to the memory controller. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种存储器系统，其中存储器控制器控制串行互连配置内的存储器件。解决方案：存储器控制器包括：用于发送存储器命令的输出端口; 以及用于接收与请求存储器响应的存储器命令相关的存储器响应的输入端口。每个存储器件包括诸如NAND型闪速存储器，NOR型闪速存储器，RAM和静态RAM的存储器。每个存储器命令特定于目标存储器件的存储器类型。通过互连提供存储器命令和存储器响应的数据路径。给定的存储器命令遍历存储器件以达到串行互连配置的期望的存储器件。当接收时，期望的存储器件执行给定的存储器命令，并将存储器响应发送到下一个存储器件。存储器响应被传送到存储器控制器。版权所有（C）2011，JPO＆INPIT

44. 发明专利

JP2011028786A Apparatus and method for capturing serial input data 有权
标题翻译：用于捕获串行输入数据的装置和方法
公开(公告)号：JP2011028786A
公开(公告)日：2011-02-10
申请号：JP2010252824
申请日：2010-11-11
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： PYEON HONG BEOM , OH HAK JUNE
IPC分类号： G06F13/16
CPC分类号： G11C5/066 , G06F13/1673 , G06F13/28 , G11C7/10 , G11C7/1078 , G11C7/1093 , G11C2207/107
摘要： PROBLEM TO BE SOLVED: To provide a method to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency in a serial input data processing apparatus.
SOLUTION: Individual bytes of serial bits of a pre-defined sequence are latched and bit streams are temporarily stored together with multiple clocks. The temporary storing is conducted before transferring byte information to assigned address registers to register the address. The address registration and the data registration are performed by latching all bit streams of the serial input at the leading edges of a plurality of clocks. While performing a high frequency operation (e.g., 1 GHz or 1 ns cycle time), no additional registers are required for storing bit data during command interpretation with enough time margins between the command bit stream interpretation and next bit data stream.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种在串行输入数据处理装置中在命令解码器中以高频执行命令解释时捕获串行数据而不丢失单个位的方法。解决方案：预定义序列的串行位的各个字节被锁存，并且位流与多个时钟临时存储在一起。在将字节信息传送到分配的地址寄存器之前进行临时存储以注册地址。通过在多个时钟的前沿锁存串行输入的所有比特流来执行地址登记和数据登记。在执行高频操作（例如，1GHz或1ns周期时间）期间，在命令解释期间，在命令比特流解释和下一个比特数据流之间具有足够的时间余量，不需要额外的寄存器来存储比特数据。版权所有（C）2011，JPO＆INPIT

45. 发明专利

JP2011019217A Network combining wired and non-wired segments 有权
标题翻译：网络组合有线和非有线部分
公开(公告)号：JP2011019217A
公开(公告)日：2011-01-27
申请号：JP2010149028
申请日：2010-06-30
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： BINDER YEHUDA
IPC分类号： H04B7/15 , H04M1/738 , H01R13/60 , H04B1/40 , H04B3/54 , H04J1/00 , H04L12/28 , H04L12/56 , H04L12/64 , H04L12/66 , H04M11/00 , H04M11/06
CPC分类号： H04L12/2838 , H04B3/542 , H04B2203/5445 , H04L12/28 , H04L12/2803 , H04L12/2832 , H04L12/6418 , H04L12/66 , H04L2012/2841 , H04L2012/2843 , H04L2012/2845 , H04W4/04 , H04W4/18 , H04W16/20 , H04W80/00 , H04W84/12 , H04W84/14 , H04W92/02 , Y02B70/325 , Y02D70/00 , Y02D70/142 , Y04S20/228
摘要： PROBLEM TO BE SOLVED: To allow integrated communication of data units connected by wires and data units connected without wires.SOLUTION: The present invention relates to a local area network 60 including both wired 5 and non-wired segments 53. The wired segments are based on new or existing wires 5a, 5b, 5c, 5d, 5e, wherein access to the wires is provided by means of outlets 61a, 61d, such as a telephone system, electrical power distribution system or cable television wiring system. The non-wired segments are based on communication using radio waves, sound or light. The wired and non-wired segments interface in the outlet, using a module 50 that serves as a mediator between the segments. The module can be integrated into the outlet, partially housed in the outlet, or attached externally to the outlet.
摘要翻译：要解决的问题：允许通过电线和数据单元连接的数据单元的集成通信无连接线。解决方案：本发明涉及包括有线5和非有线段53的局域网60.有线段基于在新的或现有的导线5a，5b，5c，5d，5e上，其中通过诸如电话系统，配电系统或有线电视布线系统的出口61a，61d提供对电线的接入。无线段基于使用无线电波，声音或光的通信。有线和非有线段在插座中接口，使用模块50，该模块50用作段之间的调解器。该模块可以集成到出口中，部分容纳在出口中，或者外部连接到出口。

46. 发明专利

JP2010283887A Distributed serial control system 有权
标题翻译：分布式串行控制系统
公开(公告)号：JP2010283887A
公开(公告)日：2010-12-16
申请号：JP2010199774
申请日：2010-09-07
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： BINDER YEHUDA
IPC分类号： H04B3/00 , H04B3/54 , H04L12/28 , H04Q9/00
摘要： PROBLEM TO BE SOLVED: To provide a distributed topology wherein each cell can be controlled via control logic stored integrally therein instead of, or in addition to, an external control manager and which allows serial connection of cells so as thereby to reduce cabling.
SOLUTION: A network topology allowing distributed sensing, control and communication, includes: a power source; a plurality of line-Powered, Serially connected Intelligent Cells (PSICs) coupled to the power source and to each other via respective communication channels comprising at least two electrical conductors; an address mean for uniquely addressing each of the PSICs; and at least one payload element coupled to one of the PSICs for operating in accordance with control logic embedded in or fed to the corresponding PSIC.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种分布式拓扑，其中每个小区可以通过一体地存储在其中的控制逻辑来控制，而不是外部控制管理器，或者除了外部控制管理器之外，并且允许小区的串行连接，从而减少布线。解决方案：允许分布式感测，控制和通信的网络拓扑结构包括：电源; 通过包括至少两个电导体的各个通信信道耦合到电源并且彼此耦合的多个线路供电的，串行连接的智能电池（PSIC）; 用于唯一地寻址每个PSIC的地址; 以及耦合到所述PSIC中的一个的至少一个有效载荷元件，用于根据嵌入或馈送到对应的PSIC的控制逻辑进行操作。版权所有（C）2011，JPO＆INPIT

47. 发明专利

JP2010193493A Initialization circuit for delay locked loop 有权
标题翻译：延迟锁定环路的初始化电路
公开(公告)号：JP2010193493A
公开(公告)日：2010-09-02
申请号：JP2010086336
申请日：2010-04-02
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： MAI TONY
IPC分类号： H03L7/081 , H03K5/13 , H03L7/085 , H03L7/089 , H03L7/10
CPC分类号： H03L7/10 , H03L7/0812 , H03L7/0891
摘要： PROBLEM TO BE SOLVED: To provide an initialization circuit for a delay locked loop. SOLUTION: The initialization circuit in a delay locked loop ensures that after power-up or other reset, clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供用于延迟锁定环路的初始化电路。解决方案：延迟锁定环路中的初始化电路确保在上电或其他复位后，相位检测器以适当的顺序接收时钟沿，以便正常工作。在延迟锁定环路复位之后，初始化电路确保在使相位检测器增加（或减小）延迟线中的延迟之前，接收到参考时钟的至少一个边沿。在接收到反馈时钟的至少一个边缘之后，初始化电路使相位检测器能够减小（或增加）延迟线中的延迟。版权所有（C）2010，JPO＆INPIT

48. 发明专利

JP2010104037A Telephone outlet and system for local area network over telephone line 有权
标题翻译：用于电话线路上的局域网的电话出口和系统
公开(公告)号：JP2010104037A
公开(公告)日：2010-05-06
申请号：JP2010014196
申请日：2010-01-26
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： BINDER YEHUDA
IPC分类号： H04M1/738 , H04M11/06 , H01R24/58 , H04L12/28 , H04M11/00
CPC分类号： H04M7/0003 , H04L12/2803 , H04L12/2838 , H04L2012/2843 , H04L2012/2845 , H04L2012/285 , H04M11/062
摘要： PROBLEM TO BE SOLVED: To provide a method and a device for upgrading a telephone line wiring system for providing both an analog telephone communication service and a local area network. SOLUTION: Local area networks 70, 80, 90, 110, 112 use telephone wiring in a residence or the other building simultaneously with a telephony signal by using network outlets 31a, 31b, 31c, 31d having telephone connectors 14a, 14b, 14c and data connectors 113a, 113d allowing the connection of data terminal equipment to the network. The network outlets use high-pass filters 22a, 22b, 22c to access the high-frequency band across media, whereby the standard telephone service uses low-pass filters to access the low-frequency voice/analog telephony band across the same media. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于升级用于提供模拟电话通信服务和局域网的电话线路布线系统的方法和装置。解决方案：局域网70,80,90,110,112通过使用具有电话连接器14a，14b的网络出口31a，31b，31c，31d，在住宅或另一建筑物中与电话信号同时使用电话线路， 14c和数据连接器113a，113d，允许数据终端设备连接到网络。网络出口使用高通滤波器22a，22b，22c来访问跨越媒体的高频带，由此标准电话业务使用低通滤波器来访问跨相同媒体的低频语音/模拟电话频带。版权所有（C）2010，JPO＆INPIT

49. 发明专利

JP2008092582A A method and apparatus for adaptive data compression 审中-公开
标题翻译：自适应数据压缩的方法和装置
公开(公告)号：JP2008092582A
公开(公告)日：2008-04-17
申请号：JP2007266759
申请日：2007-10-12
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレイテッド
发明人： MOURAD ABDAT
IPC分类号： H03M7/40 , H03M7/42 , H03M7/30
CPC分类号： H03M7/3088
摘要： PROBLEM TO BE SOLVED: To provide a method and an apparatus for performing adaptive data compression. SOLUTION: Each time an unknown symbol is encoded by an encoder, the encoder adds the symbol to a dictionary and transmits it in plain in the encoded string. The state of a prefix bit preceding the code word indicates whether the code word is a plain symbol or an index of a symbol or string of symbols stored in the dictionary. If the code word stores a symbol in plain, a decoder learns the symbol by adding a sequence of symbols resulting from the concatenation of predecoded symbols and the first symbol of the currently decoded symbol and by adding the symbol to its dictionary. If the code word stores an index, the decoder decodes the code word by extracting the symbol or sequence of symbols stored in the dictionary at the respective index in the dictionary. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于执行自适应数据压缩的方法和装置。解决方案：每当编码器对未知符号进行编码时，编码器将符号添加到字典中，并以编码字符串的形式将其传输。代码字之前的前缀位的状态指示代码字是否是存储在字典中的符号或符号串的简单符号或索引。如果代码字以简单的方式存储符号，则解码器通过将从预解码符号的连接和当前解码的符号的第一符号产生的符号序列相加并通过将符号添加到其字典来学习符号。如果码字存储索引，则解码器通过在字典中的相应索引处提取存储在字典中的符号或符号序列来解码码字。版权所有（C）2008，JPO＆INPIT

50. 发明专利

JPH08315568A METHOD FOR DETECTION AND RESTORATION OF MULTILEVEL DRUM 失效
公开(公告)号：JPH08315568A
公开(公告)日：1996-11-29
申请号：JP35293295
申请日：1995-12-29
申请人： MOSAID TECHNOLOGIES INC
发明人： GILLINGHAM PETER B
IPC分类号： G11C11/401 , G11C11/56
摘要： PROBLEM TO BE SOLVED: To densely constitute a dynamic random access memory by selectively connecting the memory to each sub-bit line through a switch so that the capacitance of each sub-bit line connected to a dummy capacitor can match the capacitance of a sub-bit line connected to a storage capacitor. SOLUTION: The electric charges stored in a storage capacitor CS are damped on a sub-bit line BL* without connecting the dummy cell of a transistor TD to a capacitor CD and on a sub-bit line BR* by connecting the dummy cell to the capacitor CD and detecting voltages for separately detecting code bits and amplitude bits expressing multilevel stored charges are provided. A left-side sense amplifier 100 detects the code bits and a right-side sense amplifier 102 detects the amplitude bits. The code and amplitude bits are commonly used appropriately for reproducing the voltage which is restored in the storage capacitor CD. Therefore, a dynamic random access memory can be constituted at a high density.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式