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41. 发明申请

US20070126467A1 Test device for on die termination 失效
标题翻译：芯片端接测试装置
公开(公告)号：US20070126467A1
公开(公告)日：2007-06-07
申请号：US11322283
申请日：2005-12-29
申请人： Kyung-Hoon Kim
发明人： Kyung-Hoon Kim
IPC分类号： H03K19/003
CPC分类号： G11C29/02 , G01R31/31715 , G01R31/318511 , G11C29/022 , G11C29/028 , G11C29/50008 , H04L25/0278 , H04L25/0298
摘要： An on die termination (ODT) test device includes: a control unit for selectively activating a plurality of pull-up signals and a plurality of pull-down signals by performing a logic operation to an ODT control signal for controlling a resistor of a termination terminal, an off chip driver (OCD) control signal for adjusting an impedance of an output terminal, a plurality of ODT test signals for measuring a termination resistance of the termination terminal and a plurality of ODT signals having a different resistance; and a pull-up/pull-down unit for selectively driving a plurality of pull-up drivers and a plurality of pull-down drivers according to the pull-up signals and the pull-down signals in order to output a corresponding resistance of the output terminal at a read operation mode.
摘要翻译：芯片终端（ODT）测试装置包括：控制单元，用于通过对ODT控制信号执行逻辑操作来选择性地激活多个上拉信号和多个下拉信号，以控制终端终端，用于调整输出端子的阻抗的芯片外驱动器（OCD）控制信号，用于测量终端终端的终端电阻的多个ODT测试信号和具有不同电阻的多个ODT信号; 以及上拉/下拉单元，用于根据上拉信号和下拉信号选择性地驱动多个上拉驱动器和多个下拉驱动器，以输出相应的电阻输出端子处于读操作模式。

42. 发明申请

US20070070717A1 Semiconductor memory device for adjusting impedance of data output driver 有权
标题翻译：用于调整数据输出驱动器阻抗的半导体存储器件
公开(公告)号：US20070070717A1
公开(公告)日：2007-03-29
申请号：US11319615
申请日：2005-12-29
申请人： Kyung-Hoon Kim
发明人： Kyung-Hoon Kim
IPC分类号： G11C7/06
CPC分类号： G11C7/1051 , G11C7/1048 , G11C7/106 , G11C7/1069 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2207/105 , G11C2207/2254
摘要： An apparatus for comparing inputted signals by removing an offset voltage during adjusting an output impedance of a semiconductor memory device, includes a voltage comparator for comparing a first input signal applied to its positive input node with a second input signal applied to its negative input node to output a first output signal to its positive output node and its second output signal to a negative output node; a switched capacitive unit for removing an offset voltage occurred in the positive input node, the negative input node, the positive output node and the negative output node of the voltage comparator; and a latch unit for latching the first output signal and the second output signal.
摘要翻译：一种用于在调整半导体存储器件的输出阻抗期间去除偏移电压来比较输入信号的装置，包括电压比较器，用于将施加于其正输入节点的第一输入信号与施加到其负输入节点的第二输入信号进行比较，将第一输出信号输出到其正输出节点并将其第二输出信号输出到负输出节点; 用于去除电压比较器的正输入节点，负输入节点，正输出节点和负输出节点中发生的偏移电压的开关电容单元; 以及用于锁存第一输出信号和第二输出信号的锁存单元。

43. 发明申请

US20070069779A1 Delay locked loop circuit 有权
标题翻译：延时锁定回路电路
公开(公告)号：US20070069779A1
公开(公告)日：2007-03-29
申请号：US11478191
申请日：2006-06-30
申请人： Kyung-Hoon Kim
发明人： Kyung-Hoon Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0805 , H03L7/087
摘要： A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.
摘要翻译：延迟锁定环通过使用具有比DLL输出时钟更高级的相位的输出时钟来增加延迟锁定环的操作余量。时钟延迟补偿块接收外部时钟信号从而产生第一多时钟和第二多时钟。相位控制块将第一多时钟与第二多个时钟进行比较，以产生控制移位操作的相位控制信号。多相延迟控制块基于相位控制信号执行移位操作，以控制时钟延迟补偿块。

44. 发明申请

US20070069777A1 DLL driver control circuit 有权
标题翻译： DLL驱动控制电路
公开(公告)号：US20070069777A1
公开(公告)日：2007-03-29
申请号：US11478082
申请日：2006-06-30
申请人： Kyung-Hoon Kim
发明人： Kyung-Hoon Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0805
摘要： A Delay Locked Loop (DLL) driver control circuit is capable of reducing an amount of current consumption by preventing the output of unnecessary clocks. The DLL driver control circuit includes a DLL driver for driving a DLL clock and a DLL driver controller for generating a control signal to control an operation of the DLL driver in response to a signal having information associated with an active mode. The DLL driver controller is provided with a counter for counting the DLL clock to produce a count a setting value having a plurality of bits and generating an activated equal signal if the two values are the same, and an SR latch for accepting the equal signal and the signal having the information associated with the active mode to provide the control signal.
摘要翻译：延迟锁定环（DLL）驱动器控制电路能够通过防止不必要的时钟的输出来减少电流消耗的量。 DLL驱动器控制电路包括用于驱动DLL时钟的DLL驱动器和用于产生用于响应于具有与活动模式相关联的信息的信号来控制DLL驱动程序的操作的DLL驱动器控制器。 DLL驱动器控制器设置有用于对DLL时钟进行计数以产生具有多个位的设置值的计数器，并且如果两个值相同则产生激活的等信号;以及SR锁存器，用于接受相等的信号和所述信号具有与所述活动模式相关联的信息以提供所述控制信号。

45. 发明申请

US20070040174A1 Thin film transistor substrate and fabrication thereof 有权
标题翻译：薄膜晶体管基板及其制造
公开(公告)号：US20070040174A1
公开(公告)日：2007-02-22
申请号：US11506740
申请日：2006-08-18
申请人： Il-gon Kim , Tae-hyeong Park , Kook-chul Moon , Chul-ho Kim , Kyung-hoon Kim , Su-kyoung Kim
发明人： Il-gon Kim , Tae-hyeong Park , Kook-chul Moon , Chul-ho Kim , Kyung-hoon Kim , Su-kyoung Kim
IPC分类号： H01L29/04
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/127 , H01L29/66757
摘要： A thin film transistor substrate having a semiconductor layer including a low concentration region and a source region/drain region adjacent to the low concentration region at both sides of a channel region made of polysilicon; a gate insulating layer and a conductive layer on the substrate the conductive layer patterned to form a gate electrode.
摘要翻译：一种薄膜晶体管基板，具有包括低浓度区域和与由多晶硅制成的沟道区域两侧的低浓度区域相邻的源极区域/漏极区域的半导体层; 栅极绝缘层和导电层，导电层被图案化以形成栅电极。

46. 发明授权

US07176761B2 Apparatus and method for receiving inputted signal 有权
标题翻译：用于接收输入信号的装置和方法
公开(公告)号：US07176761B2
公开(公告)日：2007-02-13
申请号：US11145917
申请日：2005-06-07
申请人： Kyung-Hoon Kim
发明人： Kyung-Hoon Kim
IPC分类号： H03F3/45
CPC分类号： H03K21/026
摘要： An input signal receiver of a semiconductor device includes a gain control unit for outputting a gain control signal and a variable gain amplifier for amplifying external clock in response to the gain control signal, wherein the gain control signal determines a gain of the variable gain amplifier. Further, the input signal receiver includes a buffer whose input terminal is connected to an output terminal of the variable gain amplifier and output terminal is connected to another element of the semiconductor device.
摘要翻译：半导体器件的输入信号接收器包括用于输出增益控制信号的增益控制单元和响应于增益控制信号放大外部时钟的可变增益放大器，其中增益控制信号确定可变增益放大器的增益。此外，输入信号接收机包括缓冲器，其输入端连接到可变增益放大器的输出端，输出端连接到半导体器件的另一元件。

47. 发明申请

US20060132236A1 Apparatus and method for receiving inputted signal 有权
标题翻译：用于接收输入信号的装置和方法
公开(公告)号：US20060132236A1
公开(公告)日：2006-06-22
申请号：US11145917
申请日：2005-06-07
申请人： Kyung-Hoon Kim
发明人： Kyung-Hoon Kim
IPC分类号： H03F3/45
CPC分类号： H03K21/026
摘要： An input signal receiver of a semiconductor device includes a gain control unit for outputting a gain control signal and a variable gain amplifier for amplifying external clock in response to the gain control signal, wherein the gain control signal determines a gain of the variable gain amplifier. Further, the input signal receiver includes a buffer whose input terminal is connected to an output terminal of the variable gain amplifier and output terminal is connected to another element of the semiconductor device.
摘要翻译：半导体器件的输入信号接收器包括用于输出增益控制信号的增益控制单元和响应于增益控制信号放大外部时钟的可变增益放大器，其中增益控制信号确定可变增益放大器的增益。此外，输入信号接收机包括缓冲器，其输入端连接到可变增益放大器的输出端，输出端连接到半导体器件的另一元件。

48. 发明授权

US06987408B2 Digital delay locked loop and control method thereof 有权
标题翻译：数字延迟锁定环及其控制方法
公开(公告)号：US06987408B2
公开(公告)日：2006-01-17
申请号：US10745745
申请日：2003-12-23
申请人： Kyung-Hoon Kim
发明人： Kyung-Hoon Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/089
摘要： There is provided a digital delay locked loop (DLL) which is capable of minimizing a jitter by predicting and detecting a maximum jitter timing. The digital delay locked loop includes: a clock generator for generating a source clock and a reference clock; a delay line provided with a plurality of unit delays, for delaying the source clock by a predetermined time; a delay model for reflecting a delay time of an actual internal circuit to an output of the delay line; a phase comparator for comparing a phase of the reference clock with a phase of a feedback clock outputted from the delay model; a jitter detector for detecting a maximum jitter timing in response to a phase comparison signal outputted from the phase comparator and generating a multi-delay enable signal; and a delay controller for controlling a delay amount of the delay line by unit-delay unit or multi-delay unit in response to the phase comparison signal and the multi-delay enable signal.
摘要翻译：提供了数字延迟锁定环（DLL），其能够通过预测和检测最大抖动定时来最小化抖动。数字延迟锁定环包括：用于产生源时钟和参考时钟的时钟发生器; 具有多个单位延迟的延迟线，用于将源时钟延迟预定时间; 用于将实际内部电路的延迟时间反映到延迟线的输出的延迟模型; 相位比较器，用于将参考时钟的相位与从延迟模型输出的反馈时钟的相位进行比较; 抖动检测器，用于响应于从相位比较器输出的相位比较信号检测最大抖动定时，并产生多延迟使能信号; 以及延迟控制器，用于响应于相位比较信号和多延迟使能信号，通过单位延迟单元或多延迟单元来控制延迟线的延迟量。

49. 发明授权

US5859760A Microelectronic capacitors having tantalum pentoxide dielectrics and oxygen barriers 失效
标题翻译：具有五氧化二钽电介质和氧气屏障的微电子电容器
公开(公告)号：US5859760A
公开(公告)日：1999-01-12
申请号：US843799
申请日：1997-04-21
申请人： In-sung Park , Kyung-hoon Kim
发明人： In-sung Park , Kyung-hoon Kim
IPC分类号： H01L27/04 , H01L21/02 , H01L21/31 , H01L21/316 , H01L21/318 , H01L21/822 , H01G4/06
CPC分类号： H01L28/40
摘要： A microelectronic capacitor is formed by nitrating the surface of a conducting electrode on a microelectronic substrate. The nitrated surface of the conductive electrode is then oxidized. The nitrating and oxidizing steps collectively form a film of silicon oxynitride on the conductive electrode. A tantalum pentoxide film is then formed on the oxidized and nitrated surface of the conductive electrode. The tantalum pentoxide film may then be thermally treated in the presence of oxygen gas. High performance microelectronic capacitors are thereby provided.
摘要翻译：通过在微电子衬底上硝化导电电极的表面形成微电子电容器。然后将导电电极的硝化表面氧化。硝化和氧化步骤在导电电极上共同形成氮氧化硅膜。然后在导电电极的氧化和硝化表面上形成五氧化二钽膜。然后可以在氧气存在下对五氧化钽膜进行热处理。从而提供高性能微电子电容器。

50. 发明授权

US10370787B2 Control method of washing machine 有权
公开(公告)号：US10370787B2
公开(公告)日：2019-08-06
申请号：US13320758
申请日：2010-08-31
申请人： Sun Cheol Bae , Ja In Koo , Jae Hyeok Choi , Han Su Jung , Kyung Hoon Kim
发明人： Sun Cheol Bae , Ja In Koo , Jae Hyeok Choi , Han Su Jung , Kyung Hoon Kim
IPC分类号： D06F39/00 , D06F35/00 , D06F33/02
摘要： A control method of a washing machine determines the amount of laundry placed in a drum, verifies whether the measured amount of laundry is accurate, and sets control data in the washing machine based on the verified amount of laundry. Also the control method of the washing machine corrects control data set according to the amount of laundry based on kind of the laundry classified according to absorptance of the laundry.

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