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    • 47. 发明授权
    • Semiconductor integrated circuit and driving method using comparator feedback loop to switch subtraction bypass circuit
    • 半导体集成电路和驱动方法使用比较器反馈回路来切换减法旁路电路
    • US06259393B1
    • 2001-07-10
    • US09105258
    • 1998-06-26
    • Katsuhisa OgawaTadahiro OhmiTadashi Shibata
    • Katsuhisa OgawaTadahiro OhmiTadashi Shibata
    • H03M138
    • H03M1/403
    • In order to solve the problem of increase in circuit scale and increase in power consumption due to use of a DA converter, a semiconductor integrated circuit comprises a signal amplifier 2, 10 capable of switching of a gain to 1 or 2, an arithmetic processor 7, 9 for performing a subtraction process of a reference voltage from an input signal to output a result thereof or for outputting the input signal without performing the subtraction process, a switch 8 whose one switch terminal is connected to a signal input terminal, whose other switch terminal is connected to an output side of sample hold circuits 5, 6, and whose common terminal is connected to an input side of the arithmetic processor, a comparator 3 for comparing an output from the signal amplifier with the reference voltage to binarize the output, and a switch 11 for connecting an output side of the signal amplifier to an input side of the sample hold circuits, wherein the arithmetic processor carries out a changeover between the operation of performing the subtraction process of the reference voltage from the input signal to output the result and the operation of outputting the input signal without performing the subtraction process, based on an output from the comparator, thereby decreasing the circuit scale and substantially eliminating occurrence of an error.
    • 为了解决由于使用DA转换器导致的电路规模增加和功耗增加的问题,半导体集成电路包括能够将增益切换为1或2的信号放大器2,10,运算处理器7 9,用于从输入信号执行参考电压的减法处理以输出其结果或用于在不执行减法处理的情况下输出输入信号;开关8,其一个开关端子连接到信号输入端子,其另一个开关 端子连接到采样保持电路5,6的输出侧,并且其公共端连接到算术处理器的输入侧;比较器3,用于将来自信号放大器的输出与参考电压进行比较,以二值化输出; 以及用于将信号放大器的输出侧连接到采样保持电路的输入侧的开关11,其中,算术处理器执行 基于比较器的输出,从输入信号执行参考电压的减法处理以输出结果和输出输入信号的操作而不执行减法处理的操作,从而减小电路规模并基本上消除发生 的错误。
    • 49. 发明授权
    • Semiconductor integrated circuit utilizing insulated gate type
transistors
    • 采用绝缘栅型晶体管的半导体集成电路
    • US6100741A
    • 2000-08-08
    • US110012
    • 1998-07-02
    • Katsuhisa OgawaTadahiro OhmiTadashi Shibata
    • Katsuhisa OgawaTadahiro OhmiTadashi Shibata
    • G06G7/16G06G7/163G06F7/44
    • G06G7/163
    • For raising the accuracy of analog multiplication, a gate-drain (G-D) connection point of transistor (Tr) whose gate-drain (G-D) are shorted and whose source is connected to ground potential is connected to a source of second Tr whose G-D are shorted, a first input signal current source is connected to a G-D connection point of the second Tr, a G-D connection point of third Tr whose G-D are shorted and whose source is connected to the ground potential is connected to a source of fourth Tr whose G-D are shorted, a second input signal current source is connected to a G-D connection point of the fourth Tr, the G-D connection points of the second and fourth Tr's are connected to first and second capacitors respectively, outputs of the first and second capacitors are connected to each other and to a gate of fifth Tr to form a floating point, a source of the fifth Tr is connected to the ground potential, and a drain current of the fifth Tr is an operation output.
    • 为了提高模拟倍增的精度,其栅极漏极(GD)短路并且其源极连接到地电位的晶体管(Tr)的栅极 - 漏极(GD)连接点连接到第二Tr的源极,其中GD为 短路时,第一输入信号电流源连接到第二Tr的GD连接点,GD短路的第三Tr的GD连接点和其源极连接到地电位,连接到第四Tr的源,其中GD 短路,第二输入信号电流源连接到第四Tr的GD连接点,第二和第四Tr的GD连接点分别连接到第一和第二电容器,第一和第二电容器的输出连接到 彼此并且连接到第五Tr的栅极以形成浮点,第五Tr的源极连接到地电位,并且第五Tr的漏极电流是操作输出。