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41. 发明申请

US20070268762A1 Semiconductor memory and method for testing the same 有权
标题翻译：半导体存储器及其测试方法
公开(公告)号：US20070268762A1
公开(公告)日：2007-11-22
申请号：US11797699
申请日：2007-05-07
申请人： Kaoru Mori
发明人： Kaoru Mori
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/16 , G11C2029/1804
摘要： A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time and by which a test cost is reduced and a method for testing such a semiconductor memory. The plurality of CRs hold operation mode information. When a CR control circuit detects write commands to write to an address for register access or read commands to read from the address for register access in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command by which write operation or read operation does not occur, in response to a control signal from the outside. In addition, the command generation section regenerates the test start command each time the plurality of CRs are updated. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads, the code represented by part of an address inputted at the time of the test start command being sent.
摘要翻译：一种半导体存储器，其中在测试时间内在多个CR中设置任意操作模式信息，并且测试成本降低，并且测试这种半导体存储器的方法。多个CR保持操作模式信息。当CR控制电路检测写入命令以写入寄存器访问的地址或读取命令以按预定顺序从地址读取寄存器访问时，CR控制电路更新在多个CR中的每一个的操作模式信息时分基础。响应于来自外部的控制信号，命令生成部分生成写入命令，读取命令或者不发生写入操作或读取操作的测试开始命令。另外，每当更新多个CR时，命令生成部重新生成测试开始命令。数据块压缩电路通过使用输入到数据块的一部分的测试数据，在将测试数据或其原始状态根据代码反转之后，将待写入的操作模式信息改变为用于其余部分的数据数据焊盘，由发送测试开始命令时输入的地址的一部分表示的代码。

42. 发明申请

US20070195620A1 Semiconductor memory 有权
公开(公告)号：US20070195620A1
公开(公告)日：2007-08-23
申请号：US11714766
申请日：2007-03-07
申请人： Kaoru Mori , Yoshiaki Okuyama
发明人： Kaoru Mori , Yoshiaki Okuyama
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/808 , G11C29/838
摘要： In order to give all memory blocks the same structure, a redundancy word line and a redundancy bit line are formed in each memory block. A redundancy column selection line is wired in common to the memory blocks. Column redundancy circuits are formed to correspond to respective memory groups each of which consists of a prescribed number of memory blocks, and become effective according to enable signals. A column redundancy selection circuit activates an enable signal according to a block address signal when all row hit signals are deactivated. When one of the row hit signals is activated, the column redundancy selection circuit activates the enable signal corresponding to the activated row hit signal. Since the column redundancy circuit for an arbitrary memory group can be made effective according to the row hit signals, failure relief efficiency can be increased without deteriorating the electric characteristic during an access operation.

43. 发明授权

US07187525B2 Magnetoresistive device and method for manufacturing same 有权
标题翻译：磁阻装置及其制造方法
公开(公告)号：US07187525B2
公开(公告)日：2007-03-06
申请号：US10497024
申请日：2003-09-19
申请人： Ken-ichi Shimura , Atsushi Kamijo , Yoshiyuki Fukumoto , Kaoru Mori
发明人： Ken-ichi Shimura , Atsushi Kamijo , Yoshiyuki Fukumoto , Kaoru Mori
IPC分类号： G11B5/39 , H01L43/08 , G11C11/16
CPC分类号： B82Y25/00 , B82Y10/00 , G11B5/3909 , H01F10/3254 , H01L43/08 , H01L43/12
摘要： The heat resistance of a magnetic resistance device utilizing the TMR effect is improved. Also, the Neel effect of the magnetic resistance device utilizing the TMR effect is restrained. The magnetic resistance device includes a first ferromagnetic layer formed of ferromagnetic material, a non-magnetic insulative tunnel barrier layer coupled to the first ferromagnetic layer, a second ferromagnetic layer formed of ferromagnetic material and coupled to the tunnel barrier layer, and an anti-ferromagnetic layer formed of anti-ferromagnetic material. The second ferromagnetic layer is provided between the tunnel barrier layer and the anti-ferromagnetic layer. A perpendicular line from an optional position of the surface of the second ferromagnetic layer passes through at least two of the crystal grains of the second ferromagnetic layer.
摘要翻译：利用TMR效应的磁阻元件的耐热性提高。此外，抑制了利用TMR效应的磁阻元件的Neel效应。磁阻装置包括由铁磁材料形成的第一铁磁层，耦合到第一铁磁层的非磁绝缘隧道势垒层，由铁磁材料形成并耦合到隧道势垒层的第二铁磁层，以及反铁磁层由反铁磁材料形成。第二铁磁层设置在隧道势垒层和反铁磁层之间。来自第二铁磁层的表面的可选位置的垂直线穿过第二铁磁层的至少两个晶粒。

44. 发明授权

US07079443B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07079443B2
公开(公告)日：2006-07-18
申请号：US10631752
申请日：2003-08-01
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C8/08
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.
摘要翻译：半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量存储单元阵列。此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

45. 发明申请

US20050276134A1 Memory device 有权
标题翻译：内存设备
公开(公告)号：US20050276134A1
公开(公告)日：2005-12-15
申请号：US11024734
申请日：2004-12-30
申请人： Kaoru Mori , Shinya Fujioka
发明人： Kaoru Mori , Shinya Fujioka
IPC分类号： G11C11/409 , G11C5/14 , G11C7/00 , G11C11/406 , G11C11/4091 , G11C11/4094 , G11C29/02
CPC分类号： G11C11/406 , G11C5/147 , G11C11/4094 , G11C29/02 , G11C29/025 , G11C29/12005 , G11C2029/5006 , G11C2211/4065 , G11C2211/4067
摘要： A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status.
摘要翻译：提供了一种存储器件，其具有：用于存储数据的存储器单元; 一个字线选择存储单元; 可选择的存储单元的位线; 预充电电源，用于向位线提供预充电电压; 预充电电路，用于将预充电电源连接到或从所述位线断开; 以及电流限制元件，用于根据操作状态至少两步地控制在预充电电源和位线之间流动的电流的大小。

46. 发明申请

US20050254321A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20050254321A1
公开(公告)日：2005-11-17
申请号：US11011114
申请日：2004-12-15
申请人： Yoshiaki Okuyama , Kaoru Mori
发明人： Yoshiaki Okuyama , Kaoru Mori
IPC分类号： G11C29/04 , G11C8/06 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/4193 , G11C11/4197 , G11C29/00 , G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C29/783
摘要： An arbiter judges which of an internal access request and an external access request takes higher priority, when the internal access request conflicts with the external access request. A redundancy judgement circuit judges which of a normal memory cell and a redundancy memory cell is accessed, in accordance with each of the internal access request and the external access request. When the arbiter gives higher priority to the internal access request, the redundancy judgement circuit carries out redundancy judgement for the external access request during internal access operation. To prevent the malfunction of a memory core, a hold circuit holds redundancy judged result, and prevents the redundancy judged result for the external access request from being transmitted to the memory core that carries out the internal access operation.
摘要翻译：当内部访问请求与外部访问请求冲突时，仲裁员会判断哪个内部访问请求和外部访问请求具有较高优先级。根据内部访问请求和外部访问请求中的每一个，冗余判断电路判断访问正常存储单元和冗余存储单元中的哪一个。当仲裁器给予内部访问请求更高的优先级时，冗余判断电路在内部访问操作期间对外部访问请求执行冗余判断。为了防止存储器核心的故障，保持电路保持冗余判断结果，并且防止外部访问请求的冗余判断结果被发送到执行内部访问操作的存储器核心。

47. 发明申请

US20050219769A1 Magnetoresistive device and method for manufacturing same 有权
标题翻译：磁阻装置及其制造方法
公开(公告)号：US20050219769A1
公开(公告)日：2005-10-06
申请号：US10497024
申请日：2003-09-19
申请人： Ken-ichi Shimura , Atsushi Kamijo , Yoshiyuki Fukumoto , Kaoru Mori
发明人： Ken-ichi Shimura , Atsushi Kamijo , Yoshiyuki Fukumoto , Kaoru Mori
IPC分类号： G11B5/39 , H01F10/12 , H01F10/30 , H01F10/32 , H01F41/18 , H01F41/20 , H01L43/08 , H01L43/12 , G11B5/33 , G11B5/127
CPC分类号： B82Y25/00 , B82Y10/00 , G11B5/3909 , H01F10/3254 , H01L43/08 , H01L43/12
摘要： The heat resistance of a magnetic resistance device utilizing the TMR effect is improved. Also, the Neel effect of the magnetic resistance device utilizing the TMR effect is restrained. The magnetic resistance device includes a first ferromagnetic layer formed of ferromagnetic material, a non-magnetic insulative tunnel barrier layer coupled to the first ferromagnetic layer, a second ferromagnetic layer formed of ferromagnetic material and coupled to the tunnel barrier layer, and an anti-ferromagnetic layer formed of anti-ferromagnetic material. The second ferromagnetic layer is provided between the tunnel barrier layer and the anti-ferromagnetic layer. A perpendicular line from an optional position of the surface of the second ferromagnetic layer passes through at least two of the crystal grains of the second ferromagnetic layer.
摘要翻译：利用TMR效应的磁阻元件的耐热性提高。此外，抑制了利用TMR效应的磁阻元件的Neel效应。磁阻装置包括由铁磁材料形成的第一铁磁层，耦合到第一铁磁层的非磁绝缘隧道势垒层，由铁磁材料形成并耦合到隧道势垒层的第二铁磁层，以及反铁磁层由反铁磁材料形成。第二铁磁层设置在隧道势垒层和反铁磁层之间。来自第二铁磁层的表面的可选位置的垂直线穿过第二铁磁层的至少两个晶粒。

48. 发明授权

US06765843B2 Semiconductor memory device with efficient buffer control for data buses 失效
标题翻译：具有数据总线高效缓冲控制的半导体存储器件
公开(公告)号：US06765843B2
公开(公告)日：2004-07-20
申请号：US10369562
申请日：2003-02-21
申请人： Kaoru Mori , Shuji Mabuchi
发明人： Kaoru Mori , Shuji Mabuchi
IPC分类号： G11C800
CPC分类号： G11C7/1069 , G11C7/1051 , G11C8/12
摘要： A semiconductor memory device includes a plurality of memory blocks, a plurality of data buses provided for the respective memory blocks, a plurality of buffer circuits which are provided for the respective memory blocks, and relay data of the data buses to connect the data buses in series, a block activation circuit which generates block selection signals corresponding to the respective memory blocks, and asserts one of the block selection signals to selectively activate one of the memory blocks, and a plurality of buffer control circuits which are provided for the respective memory blocks, one of the buffer control circuits activating a corresponding one of the buffer circuits in response to assertion of a corresponding one of the block selection signals or in response to activation of one of the buffer circuits at an adjacent one of the memory blocks that is located upstream along the data buses.
摘要翻译：半导体存储器件包括多个存储块，为各个存储块提供的多个数据总线，为各个存储块提供的多个缓冲电路，以及数据总线的中继数据，以连接数据总线系列，块激活电路，其生成对应于各个存储块的块选择信号，并且断言块选择信号之一以选择性地激活其中一个存储块;以及多个缓冲器控制电路，用于各个存储块缓冲器控制电路中的一个响应于块选择信号中对应的一个块的选择而激活对应的一个缓冲器电路，或响应于位于相邻的一个存储器块中的一个缓冲器电路的激活沿数据总线上游。

49. 发明授权

US06618320B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06618320B2
公开(公告)日：2003-09-09
申请号：US10316121
申请日：2002-12-11
申请人： Masatomo Hasegawa , Kaoru Mori , Masato Matsumiya
发明人： Masatomo Hasegawa , Kaoru Mori , Masato Matsumiya
IPC分类号： G11C800
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A semiconductor memory device is provided with a clock generation circuit that generates a first clock that has the same frequency and phase as an external clock, and a second clock that has the same frequency as the external clock but a phase a quarter phase shifted, and the first clock and the second clock are supplied to the two DDR-DRAMs as clocks so that the two DDR-DRAMs can operate in a state of being a quarter phase shifted from each other. A data output section outputs data respectively for time periods corresponding to a quarter phase from points a fixed phase behind the leading edge and the trailing edge of the first or the second clock and brings a data output circuit into a high impedance state for other time periods.
摘要翻译：半导体存储器件设置有产生与外部时钟具有相同频率和相位的第一时钟的时钟产生电路和具有与外部时钟相同频率但是相位四分之一相位偏移的第二时钟，以及第一时钟和第二时钟作为时钟提供给两个DDR DRAM，使得两个DDR-DRAM可以在相互偏移的四分之一相的状态下操作。数据输出部分分别从第一或第二时钟的前沿和后沿之后的固定相位的点分别输出对应于四分之一相位的时间段的数据，并将数据输出电路在其他时间段内变为高阻抗状态。

50. 发明授权

US06611472B2 Memory circuit for preventing rise of cell array power source 有权
标题翻译：用于防止电池阵列电源上升的存储电路
公开(公告)号：US06611472B2
公开(公告)日：2003-08-26
申请号：US09776909
申请日：2001-02-06
申请人： Ayako Kitamoto , Kaoru Mori
发明人： Ayako Kitamoto , Kaoru Mori
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C11/4074
摘要： The present invention is that, in a memory circuit comprising a cell array and peripheral circuit, the cell array power source is supplied to a circuit which operates during the power-down mode in addition to the cell array. The circuit which operates during the power-down mode is, for example, a self-refresh circuit. A dynamic memory requires refreshing operations in fixed intervals even during the power-down mode. Therefore, the self-refresh circuit is operating even during the power-down mode. Thus, by supplying the cell array power source to the self-refresh circuit, it is possible to consume a prescribed quantity of current from the cell array power source generation circuit to an extent of being able to maintain the level thereof even during the power-down mode. The cell array power source may be maintained within an appropriate voltage range thereby.
摘要翻译：本发明是在包括单元阵列和外围电路的存储电路中，除了单元阵列之外，单元阵列电源被提供给在掉电模式期间工作的电路。在掉电模式下工作的电路例如是自刷新电路。动态存储器即使在掉电模式下也需要以固定的间隔进行刷新操作。因此，即使在掉电模式下，自刷新电路也工作。因此，通过将电池阵列电源供给到自刷新电路，可以从电池阵列电源发电电路消耗规定量的电流至能够维持电平的程度，下模式。电池阵列电源可以由此保持在适当的电压范围内。

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