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41. 发明申请

US20070187749A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD 有权
标题翻译：半导体器件和制造方法
公开(公告)号：US20070187749A1
公开(公告)日：2007-08-16
申请号：US11733488
申请日：2007-04-10
申请人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
发明人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.
摘要翻译：半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

42. 发明申请

US20070013024A1 High-voltage transistor having shielding gate 有权
标题翻译：具有屏蔽门的高电压晶体管
公开(公告)号：US20070013024A1
公开(公告)日：2007-01-18
申请号：US11510584
申请日：2006-08-28
申请人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
发明人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译：半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。

43. 发明授权

US07064379B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07064379B2
公开(公告)日：2006-06-20
申请号：US10873296
申请日：2004-06-23
申请人： Hiroyuki Kutsukake , Kikuko Sugimae
发明人： Hiroyuki Kutsukake , Kikuko Sugimae
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/764 , H01L27/115 , H01L27/11519 , H01L27/11524
摘要： A nonvolatile semiconductor memory device including a memory cell and a selection transistor, and the memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate formed on the substrate via a second gate insulation film, and a pair of second diffusion layers formed in the substrate positioned on the opposite sides of the selection gate and one of which is electrically connected to one of the pair of first diffusion layers.
摘要翻译：一种包括存储单元和选择晶体管的非易失性半导体存储器件，并且所述存储单元包括经由第一栅极绝缘膜形成在半导体衬底上的浮置栅极，位于所述浮置栅极的相对侧上的一对第一扩散层和形成在所述衬底中，形成在所述浮置栅极的相对侧上的驱动所述浮置栅极的第一和第二控制栅极以及形成在所述第一和第二控制栅极与所述浮置栅极之间的栅极间绝缘膜。选择晶体管包括通过第二栅极绝缘膜形成在衬底上的选择栅极和形成在位于选择栅极的相对侧上的衬底中的一对第二扩散层，并且其中一个电连接到该对中的一个的第一扩散层。

44. 发明申请

US20050023597A1 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050023597A1
公开(公告)日：2005-02-03
申请号：US10873296
申请日：2004-06-23
申请人： Hiroyuki Kutsukake , Kikuko Sugimae
发明人： Hiroyuki Kutsukake , Kikuko Sugimae
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/11521 , H01L21/764 , H01L27/115 , H01L27/11519 , H01L27/11524
摘要： A nonvolatile semiconductor memory device including a memory cell and a selection transistor, and the memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate formed on the substrate via a second gate insulation film, and a pair of second diffusion layers formed in the substrate positioned on the opposite sides of the selection gate and one of which is electrically connected to one of the pair of first diffusion layers.
摘要翻译：一种包括存储单元和选择晶体管的非易失性半导体存储器件，并且所述存储单元包括经由第一栅极绝缘膜形成在半导体衬底上的浮置栅极，位于所述浮置栅极的相对侧上的一对第一扩散层和形成在所述衬底中，形成在所述浮置栅极的相对侧上的驱动所述浮置栅极的第一和第二控制栅极以及形成在所述第一和第二控制栅极与所述浮置栅极之间的栅极间绝缘膜。选择晶体管包括通过第二栅极绝缘膜形成在衬底上的选择栅极和形成在位于选择栅极的相对侧上的衬底中的一对第二扩散层，并且其中一个电连接到该对中的一个的第一扩散层。

45. 发明授权

US08885414B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08885414B2
公开(公告)日：2014-11-11
申请号：US13602738
申请日：2012-09-04
申请人： Hiroyuki Kutsukake
发明人： Hiroyuki Kutsukake
IPC分类号： G11C11/34 , G11C16/30 , G11C16/10 , H01L27/115 , G11C16/16 , G11C16/04
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/30 , H01L27/11546
摘要： A nonvolatile semiconductor memory device of an embodiment includes a p-type semiconductor substrate, a first P-well formed in the semiconductor substrate, and on which a plurality of memory cells is formed, an first N-well surrounding the first P-well and electrically separating the first P-well from the semiconductor substrate, a first negative voltage generation unit configured to generate a first negative voltage, a boost unit configured to boost a voltage and generate a boosted voltage, and a well voltage transmission unit connected to the first negative voltage generation unit, the boost unit, and the first P-well, and configured to switch a voltage between the first negative voltage and the boosted voltage, the voltage being applied to the first P-well.
摘要翻译：实施例的非易失性半导体存储器件包括p型半导体衬底，在半导体衬底中形成的第一P阱，并且其上形成有多个存储单元，围绕第一P阱的第一N阱以及将第一P阱与半导体衬底电分离，配置为产生第一负电压的第一负电压产生单元，被配置为升高电压并产生升压电压的升压单元，以及连接到第一P阱的第一负电压产生单元，升压单元和第一P阱，并且被配置为在第一负电压和升压电压之间切换电压，该电压被施加到第一P阱。

46. 发明申请

US20130250694A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20130250694A1
公开(公告)日：2013-09-26
申请号：US13602738
申请日：2012-09-04
申请人： Hiroyuki Kutsukake
发明人： Hiroyuki Kutsukake
IPC分类号： G11C16/10
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/30 , H01L27/11546
摘要： A nonvolatile semiconductor memory device of an embodiment includes a p-type semiconductor substrate, a first P-well formed in the semiconductor substrate, and on which a plurality of memory cells is formed, an first N-well surrounding the first P-well and electrically separating the first P-well from the semiconductor substrate, a first negative voltage generation unit configured to generate a first negative voltage, a boost unit configured to boost a voltage and generate a boosted voltage, and a well voltage transmission unit connected to the first negative voltage generation unit, the boost unit, and the first P-well, and configured to switch a voltage between the first negative voltage and the boosted voltage, the voltage being applied to the first P-well.

47. 发明申请

US20130069133A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130069133A1
公开(公告)日：2013-03-21
申请号：US13415010
申请日：2012-03-08
申请人： Yoshiko KATO , Hiroyuki KUTSUKAKE
发明人： Yoshiko KATO , Hiroyuki KUTSUKAKE
IPC分类号： H01L29/78
CPC分类号： H01L27/11558 , H01L27/11531
摘要： A semiconductor device, includes: a semiconductor substrate; a first conductivity type well and a second conductivity type well; a first active area; a second active area; a first well contact layer; a plurality of first source/drain layers; a first gate insulating film; a first gate electrode; a second well contact layer; a plurality of second source/drain layers; a second gate insulating film; and a second gate electrode. The first well contact layer is formed in the first active area at one end part in the one direction. The one end parts in each of the first active areas and in each of the second active areas are mutually on the same side.
摘要翻译：一种半导体器件，包括：半导体衬底; 第一导电类型井和第二导电类型井; 第一个活跃区域; 第二个活跃区域; 第一阱接触层; 多个第一源极/漏极层; 第一栅极绝缘膜; 第一栅电极; 第二阱接触层; 多个第二源极/漏极层; 第二栅绝缘膜; 和第二栅电极。第一阱接触层在一个方向上的一个端部的第一有源区域中形成。第一有效区域和第二有源区域中的每一个中的一端部分彼此相同。

48. 发明授权

US08400812B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08400812B2
公开(公告)日：2013-03-19
申请号：US13231510
申请日：2011-09-13
申请人： Hiroyuki Kutsukake , Kikuko Sugimae , Mitsuhiro Noguchi
发明人： Hiroyuki Kutsukake , Kikuko Sugimae , Mitsuhiro Noguchi
IPC分类号： G11C5/06 , G11C5/02 , G11C16/04
CPC分类号： G11C16/0483 , G11C5/063 , G11C8/14 , H01L27/0207 , H01L27/088 , H01L27/11519 , H01L27/11529
摘要： According to one embodiment, a semiconductor memory device includes a memory array and a peripheral circuit. The memory array has a plurality of memory cells, word lines, and bit lines, in which a first, second, and third blocks are set in the order along the bit line. The peripheral circuit has a transistor group. The transistor group includes a first transfer transistor belonging to the first block, a second transfer transistor belonging to the second block, and a third transfer transistor belonging to the third block. The first, second, and third transfer transistors share the other of a source and a drain of each. With regard to a direction in which either of the source and the drain is connected to the other in each of the first, second, and third transfer transistors, the directions of the adjacent transfer transistors are different from each other by 90° or 180°.
摘要翻译：根据一个实施例，半导体存储器件包括存储器阵列和外围电路。存储器阵列具有多个存储单元，字线和位线，其中按照位线的顺序设置第一，第二和第三块。外围电路具有晶体管组。晶体管组包括属于第一块的第一转移晶体管，属于第二块的第二转移晶体管和属于第三块的第三转移晶体管。第一，第二和第三转移晶体管共享每个的源极和漏极中的另一个。关于源极和漏极中的任一个与第一，第二和第三转移晶体管中的每一个连接到另一个的方向，相邻的转移晶体管的方向彼此相差90°或180° 。

49. 发明授权

US08294221B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08294221B2
公开(公告)日：2012-10-23
申请号：US12952637
申请日：2010-11-23
申请人： Yoshiko Kato , Hiroyuki Kutsukake , Masayuki Ichige
发明人： Yoshiko Kato , Hiroyuki Kutsukake , Masayuki Ichige
IPC分类号： H01L21/70
CPC分类号： H01L27/11521 , H01L27/11519
摘要： According to one embodiment, a semiconductor memory device includes a plurality of memory cell blocks, a plurality of first wirings, a plurality of second wirings, and a contact. Each of the memory cell blocks includes a plurality of memory cell units. Each of the plurality of memory cell units includes a plurality of memory cells and is provided in a first direction at a prescribed spacing. The plurality of memory cell blocks is arranged in a second direction intersecting with the first direction. The plurality of first wirings extends in the second direction and is provided in the first direction at a prescribed spacing. The plurality of second wirings is provided at least one of above and below the first wiring. The contact is provided at both end portions of the second wiring in the second direction and connects the first wiring to the second wiring. A width dimension of the second wiring along the first direction is larger than a width dimension of the first wiring along the first direction.
摘要翻译：根据一个实施例，半导体存储器件包括多个存储器单元块，多个第一布线，多个第二布线和一个触点。每个存储单元块包括多个存储单元单元。多个存储单元单元中的每一个包括多个存储单元，并且以规定间隔沿第一方向设置。多个存储单元块被布置在与第一方向交叉的第二方向上。多个第一配线在第二方向上延伸并且以规定间隔沿第一方向设置。多个第二布线被设置在第一布线的上方和下方中的至少一个。在第二方向的第二配线的两端设置接点，将第一配线连接到第二配线。沿着第一方向的第二布线的宽度尺寸大于沿着第一方向的第一布线的宽度尺寸。

50. 发明申请

US20120193698A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120193698A1
公开(公告)日：2012-08-02
申请号：US13234644
申请日：2011-09-16
申请人： Mitsuhiko NODA , Hiroyuki Kutsukake , Mitsuhiro Noguchi
发明人： Mitsuhiko NODA , Hiroyuki Kutsukake , Mitsuhiro Noguchi
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11543 , H01L29/42324
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes an element region, a gate insulating film, a first gate electrode, an intergate insulating film, a second gate electrode and an element isolation region. The gate insulating film is formed on the element region. The first gate electrode is formed on the gate insulating film. The intergate insulating film is formed on the first gate electrode and has an opening. The second gate electrode is formed on the intergate insulating film and in contact with the first gate electrode via the opening. The element isolation region encloses a laminated structure formed by the element region, the gate insulating film, and the first gate electrode. The air gap is formed between the element isolation region and side surfaces of the element region, the gate insulating film and the first gate electrode.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括元件区域，栅极绝缘膜，第一栅极电极，栅极间绝缘膜，第二栅极电极和元件隔离区域。栅极绝缘膜形成在元件区域上。第一栅电极形成在栅极绝缘膜上。栅极绝缘膜形成在第一栅电极上并具有开口。第二栅电极形成在栅间绝缘膜上并经由开口与第一栅电极接触。元件隔离区域包围由元件区域，栅极绝缘膜和第一栅极电极形成的层叠结构。在元件隔离区域和元件区域，栅极绝缘膜和第一栅极电极的侧表面之间形成气隙。

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