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41. 发明申请

US20140169086A1 COMMON SOURCE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：通用半导体存储器件
公开(公告)号：US20140169086A1
公开(公告)日：2014-06-19
申请号：US14105782
申请日：2013-12-13
申请人： Chan-Kyung KIM , Dong-Min KIM , Hong-Sun HWANG
发明人： Chan-Kyung KIM , Dong-Min KIM , Hong-Sun HWANG
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1675 , G11C11/1697
摘要： A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents to the common source line to compensate for a plurality of write currents concurrently input into or output from the common source line through the normal cell units.
摘要翻译：存储器件包括单元阵列和公共源极线补偿电路。单元阵列包括分别连接在多个位线和一个公共源极线之间的多个正常单元单元。公共源极线补偿电路向公共源极线提供多个补偿写入电流，以补偿通过正常单元单元同时输入到共用源极线或从共模源极线输出的多个写入电流。

42. 发明申请

US20140016404A1 MAGNETIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：磁性随机存取存储器
公开(公告)号：US20140016404A1
公开(公告)日：2014-01-16
申请号：US13937236
申请日：2013-07-09
申请人： Chan-kyung Kim , Soo-ho Cha , Dong-seok Kang , Chul-woo Park , Dong-hyun Sohn , Yun-sang Lee , Hye-jin Kim
发明人： Chan-kyung Kim , Soo-ho Cha , Dong-seok Kang , Chul-woo Park , Dong-hyun Sohn , Yun-sang Lee , Hye-jin Kim
IPC分类号： G11C11/16
CPC分类号： G11C11/165 , G11C5/025 , G11C5/04 , G11C7/1009 , G11C7/1054 , G11C7/1057 , G11C7/1081 , G11C7/222 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/5607 , G11C13/047 , G11C29/022 , G11C29/028 , G11C29/50008
摘要： A magnetic memory device such as a magnetic random access memory (MRAM), and a memory module and a memory system on which the magnetic memory device is mounted are disclosed. The MRAM includes magnetic memory cells each of which varies between at least two states according to a magnetization direction and an interface unit that provides various interface functions. The memory module includes a module board and at least one MRAM chip mounted on the module board, and further includes a buffer chip that manages an operation of the at least one MRAM chip. The memory system includes the MRAM and a memory controller that communicates with the MRAM, and may communicate an electric-to-optical conversion signal or an optical-to-electric conversion signal by using an optical link that is connected between the MRAM and the memory controller.
摘要翻译：公开了一种诸如磁性随机存取存储器（MRAM）的磁存储器件，以及其上安装有磁存储器件的存储器模块和存储器系统。 MRAM包括各自根据磁化方向在至少两个状态之间变化的磁存储单元和提供各种接口功能的接口单元。存储器模块包括模块板和安装在模块板上的至少一个MRAM芯片，还包括管理至少一个MRAM芯片的操作的缓冲芯片。存储器系统包括MRAM和与MRAM进行通信的存储器控制器，并且可以通过使用连接在MRAM和存储器之间的光学链路来传送电 - 光转换信号或光 - 电转换信号控制器。

43. 发明申请

US20130311717A1 MAGNETIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：磁性随机存取存储器
公开(公告)号：US20130311717A1
公开(公告)日：2013-11-21
申请号：US13768858
申请日：2013-02-15
申请人： Chan-kyung Kim , Dong-seok Kang , Hye-jin Kim , Chul-woo Park , Dong-hyun Sohn , Yun-sang Lee , Sang-beom Kang , Hyung-rok Oh , Soo-ho Cha
发明人： Chan-kyung Kim , Dong-seok Kang , Hye-jin Kim , Chul-woo Park , Dong-hyun Sohn , Yun-sang Lee , Sang-beom Kang , Hyung-rok Oh , Soo-ho Cha
IPC分类号： G11C11/16 , G06F12/02
CPC分类号： G11C11/165 , G06F12/0246 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.
摘要翻译：公开了一种磁性随机存取存储器（MRAM）及其存储器模块，包括该存储器模块的存储器系统及其控制方法。 MRAM包括被配置为根据磁化方向在至少两个状态之间改变的磁存储单元和支持多个操作模式的模式寄存器。

44. 发明申请

US20130064008A1 DATA READ CIRCUIT, NONVOLATILE MEMORY DEVICE COMPRISING DATA READ CIRCUIT, AND METHOD OF READING DATA FROM NONVOLATILE MEMORY DEVICE 有权
标题翻译：数据读取电路，包含数据读取电路的非易失性存储器件以及从非易失性存储器件读取数据的方法
公开(公告)号：US20130064008A1
公开(公告)日：2013-03-14
申请号：US13604688
申请日：2012-09-06
申请人： CHAN-KYUNG KIM , HONG-SUN HWANG , CHUL-WOO PARK , SANG-BEOM KANG , HYUNG-ROK OH
发明人： CHAN-KYUNG KIM , HONG-SUN HWANG , CHUL-WOO PARK , SANG-BEOM KANG , HYUNG-ROK OH
IPC分类号： G11C7/10 , G11C11/02
CPC分类号： G11C5/145 , G11C7/12 , G11C11/1673
摘要： A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit.
摘要翻译：非易失性存储器件包括非易失性单元阵列，其包括存储单元和参考单元，钳位电路电连接到存储单元并且被配置为在读取操作期间钳位施加到数据感测线的电压，以及钳位电压产生单元被配置为响应于具有基于参考单元的电平的第一电压产生钳位电压，并且将钳位电压反馈到钳位电路。

45. 发明授权

US08106716B2 Oscillator, oscillator implementations and method of generating an oscillating signal 有权
标题翻译：振荡器，振荡器实现和产生振荡信号的方法
公开(公告)号：US08106716B2
公开(公告)日：2012-01-31
申请号：US12320623
申请日：2009-01-30
申请人： Chan-kyung Kim
发明人： Chan-kyung Kim
IPC分类号： H03K3/03
CPC分类号： H03K3/354 , G11C7/22 , G11C7/222
摘要： One embodiment of the oscillator includes a first starved inverter and a second starved inverter. An inner inverter of the second starved inverter is cross-coupled to an inner inverter of the first starved inverter. The oscillator further includes a first inverter connected to output of the inner inverter of the first starved inverter, and a second inverter connected to output of the inner inverter of the second starved inverter.
摘要翻译：振荡器的一个实施例包括第一饥饿逆变器和第二饥饿逆变器。第二饥饿逆变器的内逆变器与第一饥饿逆变器的内逆变器交叉耦合。振荡器还包括连接到第一饥饿逆变器的内逆变器的输出的第一反相器和连接到第二饥饿逆变器的内逆变器的输出的第二反相器。

46. 发明申请

US20100171555A1 CIRCUIT FOR REDUCING DUTY DISTORTION IN A SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：用于减少半导体存储器件中的占空比的电路
公开(公告)号：US20100171555A1
公开(公告)日：2010-07-08
申请号：US12651725
申请日：2010-01-04
申请人： Chan-kyung Kim
发明人： Chan-kyung Kim
IPC分类号： H03F3/45
CPC分类号： H03K5/1565 , H03K3/35613
摘要： A circuit for outputting an amplified clock signal is disclosed. The circuit includes a first input terminal for inputting a first clock signal, a second input terminal for inputting a second clock signal, a first amplifier circuit for amplifying the first clock signal and outputting a first amplified clock signal at a first output terminal, and a second amplifier circuit for amplifying the second clock signal and outputting a second amplified clock signal at a second output terminal. The circuit additionally includes a level maintenance circuit connected to the first output terminal and the second output terminal. The circuit further includes an output circuit connected to the first output terminal and the second output terminal and configured to output a further amplified clock signal based on the first amplified clock signal and the second amplified clock signal. The level maintenance circuit is configured to reduce duty distortion in the further amplified clock signal.
摘要翻译：公开了一种用于输出放大的时钟信号的电路。该电路包括用于输入第一时钟信号的第一输入端，用于输入第二时钟信号的第二输入端，用于放大第一时钟信号并在第一输出端输出第一放大时钟信号的第一放大电路，第二放大器电路，用于放大第二时钟信号，并在第二输出端输出第二放大时钟信号。该电路还包括连接到第一输出端和第二输出端的电平维持电路。该电路还包括连接到第一输出端和第二输出端的输出电路，并且被配置为基于第一放大时钟信号和第二放大时钟信号输出进一步的放大时钟信号。电平维持电路被配置为减少进一步放大的时钟信号中的占空比失真。

47. 发明授权

US07656725B2 Semiconductor memory device which compensates for delay time variations of multi-bit data 失效
标题翻译：补偿多位数据的延迟时间变化的半导体存储器件
公开(公告)号：US07656725B2
公开(公告)日：2010-02-02
申请号：US11790582
申请日：2007-04-26
申请人： Chan-kyung Kim
发明人： Chan-kyung Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1087 , G11C7/1078 , G11C7/1093
摘要： A memory device compensates for delay time variations among multi-bit data. The device includes a first stage and a second stage of data storage units. The first stage of data storage units store first to nth data bits in response to a latch clock signal. The second stage of data storage units store the first to nth data contents output from the first stage of data storage units in response to a reference clock signal. The latch clock signal is obtained by delaying the reference clock signal. The latch clock signal includes first to nth sub latch signals. The sub latch signals are generated at different times according to propagation delay time periods of the corresponding first to nth data contents.
摘要翻译：存储器件补偿多位数据之间的延迟时间变化。该装置包括第一级和第二级的数据存储单元。数据存储单元的第一级响应于锁存时钟信号存储第一至第n个数据位。第二级数据存储单元响应于参考时钟信号存储从第一级数据存储单元输出的第一至第n数据内容。通过延迟参考时钟信号获得锁存时钟信号。锁存时钟信号包括第一至第N个子锁存信号。子锁存信号根据相应的第一至第n数据内容的传播延迟时间周期在不同时间产生。

48. 发明授权

US07603535B2 Low power consumption semiconductor memory device capable of selectively changing input/output data width and data input/output method 有权
标题翻译：能够选择性地改变输入/输出数据宽度和数据输入/输出方法的低功耗半导体存储器件
公开(公告)号：US07603535B2
公开(公告)日：2009-10-13
申请号：US10959114
申请日：2004-10-07
申请人： Jung-hwan Choi , Chan-kyung Kim
发明人： Jung-hwan Choi , Chan-kyung Kim
IPC分类号： G06F13/20
CPC分类号： G11C7/1066 , G11C7/1006 , G11C7/1039 , G11C7/1093
摘要： A semiconductor memory device includes a memory cell core having a plurality of memory cells; a data input/output circuit unit, which sets an input/output data width in response to input/output control signals and inputs/outputs data signals through at least some of a plurality of input/output pads; a pipelined circuit unit, which is connected to the data input/output circuit unit through input/output lines and transmits the data signals between the memory cell core and the data input/output circuit unit in synchronization with predetermined clock signals through an input/output path selected in response to pipeline enable signals; and a plurality of selection units, which are connected to the input/output lines through external common data lines and connect some of the input/output lines to the data input/output circuit unit in response to selection control signals. The semiconductor memory device and the data input/output method enable selective changes to the input/output data width, as needed, and selectively operate a pipelined circuit based on a set input/output data width.
摘要翻译：半导体存储器件包括具有多个存储单元的存储单元芯; 数据输入/输出电路单元，其响应于输入/输出控制信号设置输入/输出数据宽度，并通过多个输入/输出焊盘中的至少一些输入/输出数据信号; 一个流水线电路单元，通过输入/输出线连接到数据输入/输出电路单元，并通过输入/输出与预定的时钟信号同步地在存储单元核心和数据输入/输出电路单元之间传输数据信号响应于管道使能信号选择的路径; 以及多个选择单元，其通过外部公共数据线连接到输入/输出线，并且响应于选择控制信号将一些输入/输出线连接到数据输入/输出电路单元。半导体存储器件和数据输入/输出方法能够根据需要选择性地改变输入/输出数据宽度，并且基于设置的输入/输出数据宽度有选择地操作流水线电路。

49. 发明申请

US20070201288A1 Semiconductor memory device which compensates for delay time variations of multi-bit data 失效
公开(公告)号：US20070201288A1
公开(公告)日：2007-08-30
申请号：US11790582
申请日：2007-04-26
申请人： Chan-kyung Kim
发明人： Chan-kyung Kim
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1087 , G11C7/1078 , G11C7/1093
摘要： A memory device compensates for delay time variations among multi-bit data. The device includes a first stage and a second stage of data storage units. The first stage of data storage units store first to nth data bits in response to a latch clock signal. The second stage of data storage units store the first to nth data contents output from the first stage of data storage units in response to a reference clock signal. The latch clock signal is obtained by delaying the reference clock signal. The latch clock signal includes first to nth sub latch signals. The sub latch signals are generated at different times according to propagation delay time periods of the corresponding first to nth data contents.

50. 发明申请

US20060290397A1 Duty cycle correction circuit of delay locked loop and delay locked loop having the duty cycle correction circuit 有权
公开(公告)号：US20060290397A1
公开(公告)日：2006-12-28
申请号：US11512155
申请日：2006-08-30
申请人： Chan-kyung Kim
发明人： Chan-kyung Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03K5/133 , H03K5/1565
摘要： A duty cycle correction circuit and a delay locked loop (DLL) including the duty cycle correction circuit, are capable of controlling their operation in order to correctly analyze the cause of generation of a duty cycle error when the duty cycle error is generated in the DLL. The duty cycle correction circuit selectively outputs to a DLL core duty cycle offset information for controlling a duty cycle of an internal clock signal synchronized to an external clock signal under the control of a switching control signal. The DLL corrects the duty cycle of a reference clock signal according to the duty cycle offset information, thereby outputting a reference clock signal having a 50% duty cycle.

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