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    • 41. 发明授权
    • Configurable flash memory controller and method of use
    • 可配置的闪存控制器和使用方法
    • US07757037B2
    • 2010-07-13
    • US11060649
    • 2005-02-16
    • Ben Wei Chen
    • Ben Wei Chen
    • G06F12/00G06F13/00G06F13/28
    • G06F13/1694
    • A FLASH memory controller is disclosed. The controller comprises a microcontroller. The microcontroller including firmware for providing different mappings for different types of FLASH memory chips. The controller also includes FLASH control logic for communicating with the microcontroller and adapted to communicate via a FLASH data bus to at least one FLASH memory chip. The FLASH control logic including mapping logic for configuring the FLASH data bus based upon the type of FLASH memory chip coupled thereto. A method and system in accordance with the present invention provides the following advantages: Configurable data bus on the FLASH memory controller through software to simplify routing complexity. Configurable chip select and control bus for flexibility of FLASH memory placement. Elimination of external resistor network for layout simplicity. A scalable architecture for higher data bus bandwidth support. Auto-detection of FLASH memory type and capacity configuration.
    • 公开了一种闪速存储器控制器。 控制器包括微控制器。 微控制器包括用于为不同类型的闪速存储器芯片提供不同映射的固件。 控制器还包括用于与微控制器进行通信并适于经由FLASH数据总线与至少一个闪速存储器芯片通信的FLASH控制逻辑。 FLASH控制逻辑包括用于基于与其耦合的闪速存储器芯片的类型配置FLASH数据总线的映射逻辑。 根据本发明的方法和系统提供以下优点:通过软件在FLASH存储器控制器上配置数据总线,以简化路由复杂度。 可配置芯片选择和控制总线,实现闪存放置的灵活性。 消除外部电阻网络进行布局简化。 用于更高数据总线带宽支持的可扩展架构。 自动检测闪存类型和容量配置。
    • 42. 发明申请
    • Flash Memory Controller Utilizing Multiple Voltages and a Method of Use
    • 使用多个电压的闪存控制器和使用方法
    • US20080049510A1
    • 2008-02-28
    • US11937451
    • 2007-11-08
    • Ben Wei ChenDavid ChenDavid Sun
    • Ben Wei ChenDavid ChenDavid Sun
    • G11C16/00
    • G11C16/30G11C16/20
    • A Flash memory controller is disclosed. The Flash memory controller comprises a host interface, a Flash memory interface, controller logic coupled between the host interface the controller logic handling a plurality of voltages. The controller also includes a mechanism for allowing a multiple voltage host to interface with a high voltage or a multiple voltage Flash memory. A multiple voltage Flash memory controller in accordance with the present invention provides the following advantages over conventional Flash memory controllers: (1) a voltage host is allowed to interface with multiple Flash memory components that operate at different voltages in any combination; (2) power consumption efficiency is improved by integrating the programmable voltage regulator, and voltage comparator mechanism with the Flash memory controller; (3) External jumper selection is eliminated for power source configuration; and (4) Flash memory controller power source interface pin-outs are simplified.
    • 公开了一种闪存控制器。 闪存控制器包括主机接口,闪存接口,耦合在主机接口之间的控制器逻辑,控制器逻辑处理多个电压。 控制器还包括允许多电压主机与高电压或多电压闪存接口的机构。 根据本发明的多电压闪速存储器控制器提供了比传统闪存控制器以下的优点:(1)允许电压主机与在任何组合中以不同电压工作的多个闪存组件进行接口; (2)通过将可编程稳压器和电压比较器机构与闪存控制器集成来提高功耗效率; (3)电源配置消除外部跳线选择; 和(4)闪存控制器电源接口引脚简化。
    • 44. 发明申请
    • Serial Interface to Flash-Memory Chip Using PCI-Express-Like Packets and Packed Data for Partial-Page Writes
    • 使用类似PCI-Express的数据包和打包数据进行部分页面写入的闪存芯片的串行接口
    • US20050120163A1
    • 2005-06-02
    • US10708096
    • 2004-02-09
    • Horng-Yee ChouBen Wei Chen
    • Horng-Yee ChouBen Wei Chen
    • G06F12/00
    • G11C16/10
    • A serial flash-memory chip has a serial-bus interface to an external controller. A flash-memory block in the serial flash-memory chip can be read by the external controller sending a read-request packet over the serial bus to the serial flash-memory chip, which reads the flash memory and sends the data back in a data-payload field in a completion packet. Data in a write-request packet is written to the flash memory, and a message packet sent back over the serial bus. The serial bus can be a Peripheral Component Interconnect (PCI) Express bus with bi-directional pairs of differential lines. Packets have modified-PCI-Express headers that define the packet type and data-payload length. Vendor-defined packets can send flash commands such as reset, erase, or responses after operations such as program or erase. A serial engine and microcontroller or state machine are on the serial flash-memory chip.
    • 串行闪存芯片具有到外部控制器的串行总线接口。 串行闪速存储器芯片中的闪存块可以由外部控制器通过串行总线发送读取请求数据包到串行闪速存储器芯片读取,串行闪存芯片读取闪存并将数据发送回数据 -payload字段在完成数据包中。 写请求数据包中的数据被写入闪速存储器,并且通过串行总线发回消息数据包。 串行总线可以是具有双向差分线对的外围组件互连(PCI)Express总线。 数据包已经修改了PCI-Express头,定义了数据包类型和数据有效负载长度。 供应商定义的数据包可以在诸如编程或擦除的操作之后发送闪烁命令,例如复位,擦除或响应。 串行引擎和微控制器或状态机位于串行闪存芯片上。
    • 45. 发明申请
    • Single-Chip USB Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage
    • 单芯片USB控制器从用于存储用户的集成闪存读取上电启动代码
    • US20050120146A1
    • 2005-06-02
    • US10707277
    • 2003-12-02
    • Ben Wei ChenHorng-Yee ChouSun-Teck SeeCharles Lee
    • Ben Wei ChenHorng-Yee ChouSun-Teck SeeCharles Lee
    • G06F13/28
    • G06F13/28G06F3/0679Y02D10/14
    • A Universal-Serial-Bus (USB) single-chip flash device contains a USB flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. USB packets from a host USB bus are read by a serial engine on the USB flash microcontroller. Various routines that execute on a CPU in the USB flash microcontroller are activated in response to commands in the USB packets. A flash-memory controller in the USB flash microcontroller transfers data from the serial engine to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.
    • 通用串行总线(USB)单芯片闪存器件包含一个USB闪存单片机和闪存大容量存储块,其中包含可寻址的闪存阵列,而不是随机寻址。 来自主机USB总线的USB数据包由USB闪存单片机上的串行引擎读取。 响应于USB数据包中的命令,激活在USB闪存单片机中的CPU上执行的各种例程。 USB闪存单片机中的闪存控制器将数据从串行引擎传输到闪存大容量存储块进行存储。 不是从耦合到CPU的内部ROM引导,引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时,闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。
    • 46. 发明授权
    • Blank smart card device issuance system
    • 空白智能卡设备发行系统
    • US08839415B2
    • 2014-09-16
    • US13019180
    • 2011-02-01
    • Ben Wei Chen
    • Ben Wei Chen
    • G06F12/14H04L9/32G06Q20/34G06K19/077H04L9/08G06F21/33G06F21/44G06K17/00
    • G06K19/07716G06F21/33G06F21/445G06K2017/0041G06Q20/355H04L9/0869H04L9/0891H04L9/3226H04L9/3247H04L9/3268
    • A smart card issuance system and method are disclosed. In a first aspect a method and system for issuing a smart card device (SC) is disclosed. The method and system comprise providing an initialization phase of the SC by a manufacturer and providing an authentication phase of the SC by the manufacturer. The method and system also include deploying the SC, providing a first time authentication phase for a specific customer by the issuer (IS) after the SC is deployed and starting a first phase of the registration process of the SC for the specific customer by the issuer. The method and system further include providing another authentication phase of the SC by IS after the first time authentication; and providing of an authentication of the IS by the SC. When both the SC and IS are mutually authenticated, the IS and the specific customer are allowed to complete the registration process. In a second aspect, a data transmission process and system for a smart card device (SC) of an issuer (IS) is disclosed. The process and system comprises performing a login of the SC by a user and performing a mutual authentication of the SC and the IS. The process and system further includes establishing a session key after mutual authentication is established. The session key is used to encrypt and decrypt data for transmission between the IS and the SC.
    • 公开了一种智能卡发行系统和方法。 在第一方面,公开了一种用于发布智能卡设备(SC)的方法和系统。 该方法和系统包括由制造商提供SC的初始化阶段,并由制造商提供SC的认证阶段。 该方法和系统还包括部署SC,在SC部署之后由发行商(IS)为特定客户提供第一时间认证阶段,并且由开发者开始针对特定客户的SC的注册过程的第一阶段 。 所述方法和系统还包括:在第一次认证之后通过IS提供SC的另一认证阶段; 并由SC提供IS的认证。 当SC和IS都相互认证时,IS和特定客户可以完成注册过程。 在第二方面,公开了一种用于发行者(IS)的智能卡设备(SC)的数据传输过程和系统。 该过程和系统包括由用户执行SC的登录并执行SC和IS的相互认证。 该过程和系统还包括在相互认证建立之后建立会话密钥。 会话密钥用于对IS和SC之间传输的数据进行加密和解密。
    • 48. 发明申请
    • PRIVATE CLOUD SERVER AND CLIENT ARCHITECTURE WITHOUT UTILIZING A ROUTING SERVER
    • 私有云服务器和客户端架构,不使用路由服务器
    • US20130067550A1
    • 2013-03-14
    • US13229285
    • 2011-09-09
    • Ben Wei CHENChin-Tang YENShi-Ming Zhao
    • Ben Wei CHENChin-Tang YENShi-Ming Zhao
    • G06F21/20
    • H04L63/0272H04L29/06326H04L29/08306H04L63/029H04L63/08H04L67/10
    • A method and system for use with a public cloud network is disclosed, wherein the public cloud network includes at least one private cloud server and at least one smart client device in communication therewith. The method and system comprise setting up the at least one private cloud server and the at least one smart client device in a client server relationship. The at least one private cloud server includes a message box associated therewith. The first message box is located in the public network. The at least one smart client includes a second message box associated therewith. The second message box is located on the public network. The method includes passing session based message information between the at least one private cloud server and the at least one smart client device via the first message box and the second message box in a secure manner. The session base information is authenticated by the private cloud server and the at least one smart client device. The smart client device and the private cloud server can then communicate with each other after the session based information is authenticated.
    • 公开了一种用于公共云网络的方法和系统,其中公共云网络包括至少一个私有云服务器和与其通信的至少一个智能客户端设备。 该方法和系统包括以客户端服务器关系设置至少一个私有云服务器和至少一个智能客户端设备。 所述至少一个私有云服务器包括与其相关联的消息框。 第一个消息框位于公共网络中。 至少一个智能客户端包括与其相关联的第二消息框。 第二个消息框位于公共网络上。 该方法包括经由第一消息框和第二消息框以安全的方式在至少一个私有云服务器与至少一个智能客户端设备之间传送基于会话的消息信息。 会话基础信息由私有云服务器和至少一个智能客户端设备认证。 智能客户端设备和私有云服务器可以在基于会话的信息被认证后相互通信。
    • 49. 发明申请
    • BLANK SMART CARD DEVICE ISSUANCE SYSTEM
    • 空白智能卡设备问题系统
    • US20120198548A1
    • 2012-08-02
    • US13019180
    • 2011-02-01
    • Ben Wei CHEN
    • Ben Wei CHEN
    • H04L9/32G06K19/073
    • G06K19/07716G06F21/33G06F21/445G06K2017/0041G06Q20/355H04L9/0869H04L9/0891H04L9/3226H04L9/3247H04L9/3268
    • A smart card issuance system and method are disclosed. In a first aspect a method and system for issuing a smart card device (SC) is disclosed. The method and system comprise providing an initialization phase of the SC by a manufacturer and providing an authentication phase of the SC by the manufacturer. The method and system also include deploying the SC, providing a first time authentication phase for a specific customer by the issuer (IS) after the SC is deployed and starting a first phase of the registration process of the SC for the specific customer by the issuer. The method and system further include providing another authentication phase of the SC by IS after the first time authentication; and providing of an authentication of the IS by the SC. When both the SC and IS are mutually authenticated, the IS and the specific customer are allowed to complete the registration process. In a second aspect, a data transmission process and system for a smart card device (SC) of an issuer (IS) is disclosed. The process and system comprises performing a login of the SC by a user and performing a mutual authentication of the SC and the IS. The process and system further includes establishing a session key after mutual authentication is established. The session key is used to encrypt and decrypt data for transmission between the IS and the SC.
    • 公开了一种智能卡发行系统和方法。 在第一方面,公开了一种用于发布智能卡设备(SC)的方法和系统。 该方法和系统包括由制造商提供SC的初始化阶段,并由制造商提供SC的认证阶段。 该方法和系统还包括部署SC,在SC部署之后由发行商(IS)为特定客户提供第一时间认证阶段,并且由开发者开始针对特定客户的SC的注册过程的第一阶段 。 所述方法和系统还包括:在第一次认证之后通过IS提供SC的另一认证阶段; 并由SC提供IS的认证。 当SC和IS都相互认证时,IS和特定客户可以完成注册过程。 在第二方面,公开了一种用于发行者(IS)的智能卡设备(SC)的数据传输过程和系统。 该过程和系统包括由用户执行SC的登录并执行SC和IS的相互认证。 该过程和系统还包括在相互认证建立之后建立会话密钥。 会话密钥用于对IS和SC之间传输的数据进行加密和解密。
    • 50. 发明申请
    • DUAL-MODE WIRELESS NETWORKED DEVICE INTERFACE AND AUTOMATIC CONFIGURATION THEREOF
    • 双模无线网络设备接口及其自动配置
    • US20120102106A1
    • 2012-04-26
    • US12912614
    • 2010-10-26
    • Ben Wei CHEN
    • Ben Wei CHEN
    • G06F15/177G06F15/16G06F13/40
    • H04W76/023H04L29/12226H04L61/2015H04W76/14H04W84/18
    • A wireless networked device interface is disclosed. The wireless networked device interface comprises a central processing unit (CPU), a bus coupled to the CPU, a memory/buffer coupled to the bus, a peripheral bus interface coupled to the bus, an upstream network module coupled to the bus, a downstream network module coupled to the bus and a peripheral device. The device interface includes a nonvolatile memory (NVM) coupled to the bus. The NVM includes a configuration function which through a portable device can associate with one or more portable devices on the downstream wireless network and associate with one or more access points on the upstream wireless network. The wireless networked device as well as the access point can be discovered, selected and auto-configured through the graphic user interface of one of the portable devices on the downstream wireless network.
    • 公开了一种无线网络设备接口。 无线网络设备接口包括中央处理单元(CPU),耦合到CPU的总线,耦合到总线的存储器/缓冲器,耦合到总线的外围总线接口,耦合到总线的上游网络模块,下游 网络模块耦合到总线和外围设备。 设备接口包括耦合到总线的非易失性存储器(NVM)。 NVM包括通过便携式设备可以与下游无线网络上的一个或多个便携式设备相关联并与上游无线网络上的一个或多个接入点相关联的配置功能。 可以通过下游无线网络上的一个便携式设备的图形用户界面来发现,选择和自动配置无线网络设备以及接入点。