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41. 发明授权

US11600663B2 Memory cell and memory array select transistor 有权
公开(公告)号：US11600663B2
公开(公告)日：2023-03-07
申请号：US16740652
申请日：2020-01-13
申请人： Zeno Semiconductor, Inc.
发明人： Jin-Woo Han , Yuniarto Widjaja
IPC分类号： H01L27/24 , H01L27/11517 , H01L27/22
摘要： A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.

42. 发明申请

US20220367472A1 NAND String Utilizing Floating Body Memory Cell 有权
公开(公告)号：US20220367472A1
公开(公告)日：2022-11-17
申请号：US17868722
申请日：2022-07-19
申请人： Zeno Semiconductor, Inc.
发明人： Benjamin S. Louie , Jin-Woo Han , Yuniarto Widjaja
IPC分类号： H01L27/108 , H01L21/265 , H01L27/115 , G11C16/04 , H01L27/088 , H01L29/66 , H01L29/78 , G11C5/06 , H01L23/528 , H01L27/11524 , H01L27/1157 , G11C11/4096 , G11C11/4099 , H01L29/10
摘要： NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

43. 发明申请

US20220278104A1 Memory Cell Comprising First and Second Transistors and Methods of Operating 有权
公开(公告)号：US20220278104A1
公开(公告)日：2022-09-01
申请号：US17743248
申请日：2022-05-12
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja , Jin-Woo Han , Benjamin S. Louie
IPC分类号： H01L27/108 , H01L29/78 , H01L29/70 , G11C11/404 , H01L29/73 , G11C16/04 , G11C16/10 , H01L27/11524 , H01L27/102 , H01L29/08 , H01L29/10 , H01L29/36 , G11C16/26 , G11C16/34
摘要： Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

44. 发明申请

US20220199160A1 Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Including Resistance Change Material and Method of Operating 有权
公开(公告)号：US20220199160A1
公开(公告)日：2022-06-23
申请号：US17693751
申请日：2022-03-14
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C14/00 , G11C11/14 , G11C11/404 , G11C11/56 , G11C13/00 , H01L27/108 , H01L27/24 , H01L29/78 , H01L27/102 , H01L45/00 , G06F3/06 , G11C11/402 , G11C11/4067 , H01L27/12
摘要： Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

45. 发明申请

US20220130451A1 MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR 有权
公开(公告)号：US20220130451A1
公开(公告)日：2022-04-28
申请号：US17569417
申请日：2022-01-05
申请人： Zeno Semiconductor, Inc.
发明人： Jin-Woo Han , Neal Berger , Yuniarto Widjaja
IPC分类号： G11C11/4096 , G11C11/401 , G11C11/4076 , G11C29/50 , H01L27/108
摘要： A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

46. 发明授权

US11295813B2 Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating 有权
公开(公告)号：US11295813B2
公开(公告)日：2022-04-05
申请号：US17107904
申请日：2020-11-30
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C11/40 , G11C14/00 , G11C11/14 , G11C11/404 , G11C11/56 , G11C13/00 , H01L27/108 , H01L27/24 , H01L29/78 , H01L27/102 , H01L45/00 , G06F3/06 , G11C11/402 , G11C11/4067 , H01L27/12
摘要： Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

47. 发明授权

US11250905B2 Memory device comprising electrically floating body transistor 有权
公开(公告)号：US11250905B2
公开(公告)日：2022-02-15
申请号：US17161403
申请日：2021-01-28
申请人： Zeno Semiconductor, Inc.
发明人： Jin-Woo Han , Neal Berger , Yuniarto Widjaja
IPC分类号： G11C16/04 , G11C11/402 , G11C11/4074 , G11C11/4094 , G11C11/4096 , G11C16/08 , H01L27/108 , H01L29/73 , H01L29/78 , H01L27/102 , H01L29/70 , H01L29/788 , G11C11/401 , G11C11/4076 , G11C29/50 , G11C8/12 , G11C8/10 , G11C8/00 , G11C5/06
摘要： A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

48. 发明申请

US20210327880A1 Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor 有权
公开(公告)号：US20210327880A1
公开(公告)日：2021-10-21
申请号：US17363291
申请日：2021-06-30
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： H01L27/108 , G11C8/10 , G11C11/405 , G11C8/16 , G11C11/40 , G11C11/403 , H01L27/102 , G11C7/00 , H01Q1/22
摘要： Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

49. 发明申请

US20210257365A1 Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle 有权
公开(公告)号：US20210257365A1
公开(公告)日：2021-08-19
申请号：US17232587
申请日：2021-04-16
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： H01L27/108 , G11C11/404 , G11C11/4076 , H01L29/78 , G11C11/406 , G11C11/4096
摘要： Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state.

50. 发明申请

US20210257025A1 Memory Cells, Memory Cell Arrays, Methods of Using and Methods of Making 有权
公开(公告)号：US20210257025A1
公开(公告)日：2021-08-19
申请号：US17246953
申请日：2021-05-03
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C14/00 , H01L27/24 , H01L29/66 , G11C13/00 , H01L45/00 , G11C11/56 , G11C11/4074 , G11C11/404 , H01L27/102 , G11C11/402 , H01L27/105 , H01L29/788 , H01L29/78 , H01L27/108
摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

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