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41. 发明授权

US09164730B2 Self-timed logic bit stream generator with command to run for a number of state transitions 有权
标题翻译：具有命令的自定时逻辑比特流生成器，用于运行多个状态转换
公开(公告)号：US09164730B2
公开(公告)日：2015-10-20
申请号：US14037303
申请日：2013-09-25
申请人： Netronome Systems, Inc.
发明人： Gavin J. Stark
IPC分类号： G06F7/58
CPC分类号： G06F7/584
摘要： A bit stream having non-deterministic entropy is generated by a Self-Timed Logic Entropy Bit Stream Generator (STLEBSG). The STLEBSG includes an incrementer and a linear feedback shift register (LFSR), both implemented in self-timed logic as parts of an asynchronous state machine. In response to a command, the incrementer asynchronously increments a number of times and then stops, where the number of times is determined by command. For each increment of the incrementer, the LFSR undergoes a state transition. As the incrementer increments, the LFSR outputs the bit stream. If the command is a run repeatedly command, then after the incrementer stops the incrementer is reinitialized and then again increments the number of times. This incrementing, stopping, reinitializing, and incrementing process is repeated indefinitely. Another command causes the incrementer to be loaded. Another command causes the LFSR to be loaded.
摘要翻译：具有非确定性熵的比特流由自定时逻辑熵比特流生成器（STLEBSG）产生。 STLEBSG包括一个增量器和一个线性反馈移位寄存器（LFSR），两者均以自定时逻辑实现，作为异步状态机的一部分。响应于命令，增量器异步地增加一次次数，然后停止，其中次数由命令确定。对于增量器的每个增量，LFSR经历状态转换。随着递增器递增，LFSR输出比特流。如果命令是重复运行命令，则在增量程序停止后，增量程序将重新初始化，然后再次递增次数。这种递增，停止，重新初始化和递增过程无限期地重复。另一个命令导致加载器被加载。另一个命令导致加载LFSR。

42. 发明申请

US20150293792A1 PICOENGINE MULTI-PROCESSOR WITH TASK ASSIGNMENT 有权
标题翻译：具有任务分配的PICOENGINE多处理器
公开(公告)号：US20150293792A1
公开(公告)日：2015-10-15
申请号：US14251592
申请日：2014-04-12
申请人： Netronome Systems, Inc.
发明人： Gavin J. Stark
IPC分类号： G06F9/50 , G06F9/48 , G06F9/38
CPC分类号： G06F15/80 , G06F1/3237 , G06F1/3275 , G06F1/3287 , G06F9/30047 , G06F9/30076 , G06F9/38 , G06F9/3802 , G06F9/3877 , G06F9/3885 , G06F9/4843 , G06F9/5027 , G06F9/5038 , G06F15/8007 , G06F15/8046 , G06F15/8053 , Y02D10/128 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D10/22
摘要： A general purpose PicoEngine Multi-Processor (PEMP) includes a hierarchically organized pool of small specialized picoengine processors and associated memories. A stream of data input values is received onto the PEMP. Each input data value is characterized, and from the characterization a task is determined. Picoengines are selected in a sequence. When the next picoengine in the sequence is available, it is then given the input data value along with an associated task assignment. The picoengine then performs the task. An output picoengine selector selects picoengines in the same sequence. If the next picoengine indicates that it has completed its assigned task, then the output value from the selected picoengine is output from the PEMP. By changing the sequence used, more or less of the processing power and memory resources of the pool is brought to bear on the incoming data stream. The PEMP automatically disables unused picoengines and memories.
摘要翻译：通用PicoEngine多处理器（PEMP）包括一个分层组织的小型专用微型引擎处理器和相关存储器的池。数据输入值流被接收到PEMP上。每个输入数据值被表征，并且从表征确定任务。 Picoengines按顺序选择。当序列中的下一个微型引擎可用时，然后给出输入数据值以及相关的任务分配。 picoengine然后执行任务。输出微型引擎选择器以相同的顺序选择微型引线。如果下一个微微引擎指示它已经完成其分配的任务，则从PEMP输出所选择的微微引擎的输出值。通过改变所使用的顺序，或多或少地将该池的处理能力和存储器资源承担在输入数据流上。 PEMP自动禁用未使用的打印机和内存。

43. 发明授权

US09154468B2 Efficient forwarding of encrypted TCP retransmissions 有权
标题翻译：加密TCP重传的高效转发
公开(公告)号：US09154468B2
公开(公告)日：2015-10-06
申请号：US13737907
申请日：2013-01-09
申请人： Roelof Nico du Toit
发明人： Roelof Nico du Toit
IPC分类号： H04L29/06
CPC分类号： H04L63/0428 , H04L63/168
摘要： A network device receives TCP segments of a flow via a first SSL session and transmits TCP segments via a second SSL session. Once a TCP segment has been transmitted, the TCP payload need no longer be stored on the network device. Substantial memory resources are conserved, because the device may have to handle many retransmit TCP segments at a given time. If the device receives a retransmit segment, then the device regenerates the retransmit segment to be transmitted. A data structure of entries is stored, with each entry including a decrypt state and an encrypt state for an associated SSL byte position. The device uses the decrypt state to initialize a decrypt engine, decrypts an SSL payload of the retransmit TCP segment received, uses the encrypt state to initialize an encrypt engine, re-encrypts the SSL payload, and then incorporates the re-encrypted SSL payload into the regenerated retransmit TCP segment.
摘要翻译：网络设备经由第一SSL会话接收流的TCP片段，并经由第二SSL会话传输TCP片段。一旦TCP片段被传输，TCP有效载荷就不再需要存储在网络设备上。大量的内存资源是保守的，因为设备可能必须在给定时间处理许多重传TCP段。如果设备收到重传段，则设备重新生成要发送的重传段。存储条目的数据结构，每个条目包括用于相关联的SSL字节位置的解密状态和加密状态。该设备使用解密状态来初始化解密引擎，解密所接收的重传TCP片段的SSL有效载荷，使用加密状态初始化加密引擎，重新加密SSL有效载荷，然后将重新加密的SSL有效载荷合并到再生的重传TCP段。

44. 发明授权

US09124644B2 Script-controlled egress packet modifier 有权
标题翻译：脚本控制的出口包修饰符
公开(公告)号：US09124644B2
公开(公告)日：2015-09-01
申请号：US13941494
申请日：2013-07-14
申请人： Netronome Systems, Inc.
发明人： Chirag P. Patel , Gavin J. Stark
IPC分类号： H04L29/06 , G06F9/00
CPC分类号： H04L69/22 , G06F9/00 , G06F9/30018 , G06F9/3867 , H04L49/3063 , H04L69/04
摘要： An egress packet modifier includes a script parser and a pipeline of processing stages. Rather than performing egress modifications using a processor that fetches and decodes and executes instructions in a classic processor fashion, and rather than storing a packet in memory and reading it out and modifying it and writing it back, the packet modifier pipeline processes the packet by passing parts of the packet through the pipeline. A processor identifies particular egress modifications to be performed by placing a script code at the beginning of the packet. The script parser then uses the code to identify a specific script of opcodes, where each opcode defines a modification. As a part passes through a stage, the stage can carry out the modification of such an opcode. As realized using current semiconductor fabrication process, the packet modifier can modify 200M packets/second at a sustained rate of up to 100 gigabits/second.
摘要翻译：出口分组修饰符包括脚本解析器和处理阶段的流水线。而不是使用处理器执行出口修改，处理器以经典处理器的方式获取和解码并执行指令，而不是将数据包存储在存储器中并将其读出并修改它并将其写回来，数据包修改器流水线通过传递来处理数据包部分数据包通过管道。处理器通过将脚本代码放置在分组的开始处来识别要执行的特定出口修改。脚本解析器然后使用代码来识别操作码的特定脚本，其中每个操作码定义了一个修改。作为一个阶段，舞台可以进行这样一个操作码的修改。通过使用当前的半导体制造工艺实现，分组修改器可以以高达100吉比特/秒的持续速率修改200M分组/秒。

45. 发明授权

US09100212B2 Transactional memory that performs a direct 32-bit lookup operation 有权
标题翻译：执行直接32位查找操作的事务内存
公开(公告)号：US09100212B2
公开(公告)日：2015-08-04
申请号：US13552605
申请日：2012-07-18
申请人： Gavin J. Stark , Ron L. Swartzentruber
发明人： Gavin J. Stark , Ron L. Swartzentruber
IPC分类号： G06F12/00 , H04L12/46 , G06F12/06 , G06F9/30 , G06F15/163
CPC分类号： H04L12/4625 , G06F9/3004 , G06F12/06 , G06F15/163
摘要： A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a base address, a starting bit position, and a mask size. In response to the lookup command, the TM pulls an input value (IV). The TM uses the starting bit position and the mask size to select a portion of the IV. A first sub-portion of the portion of the IV and the base address are summed to generate a memory address. The memory address is used to read a word containing multiple result values (RVs) from memory. One RV from the word is selected using a multiplexing circuit and a second sub-portion of the portion of the IV. If the selected RV is a final value, then lookup operation is complete and the TM sends the RV to the processor, otherwise the TM performs another lookup operation based upon the selected RV.
摘要翻译：事务存储器（TM）从处理器接收总线上的查找命令。该命令包括基地址，起始位位置和掩码大小。响应于查找命令，TM拉取输入值（IV）。 TM使用起始位位置和掩码大小来选择IV的一部分。将IV的部分和基地址的第一子部分相加以生成存储器地址。存储器地址用于从存储器读取包含多个结果值（RV）的单词。使用多路复用电路和IV部分的第二子部分选择来自该单词的一个RV。如果所选的RV是最终值，则查找操作完成，并且TM将RV发送到处理器，否则TM基于所选择的RV执行另一查找操作。

46. 发明授权

US09098264B2 Transactional memory that performs a direct 24-BIT lookup operation 有权
标题翻译：执行直接24位查找操作的事务内存
公开(公告)号：US09098264B2
公开(公告)日：2015-08-04
申请号：US13552627
申请日：2012-07-18
申请人： Gavin J. Stark , Hetal Sanket Borad
发明人： Gavin J. Stark , Hetal Sanket Borad
IPC分类号： G06F12/00 , G06F9/30 , G06F12/06 , G06F15/163
CPC分类号： G06F9/3001 , G06F9/3004 , G06F9/30087 , G06F12/06 , G06F15/163
摘要： A transactional memory (TM) receives a lookup command across a bus from a processor. Only final result values are stored in memory. The command includes a base address, a starting bit position, and mask size. In response to the lookup command, the TM pulls an input value (IV). A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV and the base address are used to generate a memory address. The memory address is used to read a word containing multiple result values (RVs) from memory. One RV from the word is selected using a multiplexing circuit and a result location value (RLV) generated from the portion of the IV. A word selector circuit and arithmetic circuits are used to generate the memory address and RLV. The TM sends the selected RV to the processor.
摘要翻译：事务存储器（TM）从处理器接收总线上的查找命令。只有最终的结果值存储在内存中。该命令包括基地址，起始位位置和掩码大小。响应于查找命令，TM拉取输入值（IV）。 TM内的选择电路使用起始位位置和掩码大小来选择IV的一部分。 IV和基地址的部分用于生成内存地址。存储器地址用于从存储器读取包含多个结果值（RV）的单词。使用多路复用电路和从IV部分产生的结果位置值（RLV）来选择来自该单词的一个RV。字选择器电路和运算电路用于产生存储器地址和RLV。 TM将所选择的RV发送到处理器。

47. 发明申请

US20150089242A1 ENTROPY STORAGE RING HAVING STAGES WITH FEEDBACK INPUTS 有权
标题翻译：具有反馈输入的入口存储环
公开(公告)号：US20150089242A1
公开(公告)日：2015-03-26
申请号：US14037319
申请日：2013-09-25
申请人： Netronome Systems, Inc.
发明人： Gavin J. Stark
IPC分类号： H04L9/08
CPC分类号： G06F7/58
摘要： An entropy storage ring includes an input node, a plurality of serial-connected stages, and an output node. Each stage includes an XOR (or XNOR) circuit, a delay element having an input coupled to the XOR output, and a combinatorial circuit having an output coupled to a second input of the XOR. The combinatorial circuit may be a NAND, NOR, AND or OR gate. A first input of the XOR is the data input of the stage. The output of the delay element is the data output of the stage. A first input of the combinatorial circuit is coupled to receive an enable bit from a configuration register. A second input of the combinatorial circuit is coupled to the ring output node. In operation, a bit stream is supplied onto the ring input node. Feedback of multiple stages are enabled so that the bit stream undergoes complex permutation as it circulates.
摘要翻译：熵存储环包括输入节点，多个串联级和输出节点。每个级包括XOR（或XNOR）电路，具有耦合到XOR输出的输入的延迟元件，以及具有耦合到XOR的第二输入的输出的组合电路。组合电路可以是NAND，NOR，或或或门。 XOR的第一个输入是舞台的数据输入。延迟元件的输出是级的数据输出。组合电路的第一输入被耦合以从配置寄存器接收使能位。组合电路的第二输入耦合到环形输出节点。在操作中，位流被提供到环形输入节点上。启用多级的反馈，使得位流在其循环时经历复杂的置换。

48. 发明申请

US20150089095A1 TRANSACTIONAL MEMORY THAT SUPPORTS PUT AND GET RING COMMANDS 有权
标题翻译：支持输入和取得命令的交互式记忆
公开(公告)号：US20150089095A1
公开(公告)日：2015-03-26
申请号：US14037214
申请日：2013-09-25
申请人： Netronome Systems, Inc.
发明人： Gavin J. Stark
IPC分类号： G06F9/46 , G06F3/06
CPC分类号： G06F12/063 , G06F3/061 , G06F3/0656 , G06F3/0683 , G06F9/3004 , G06F9/3836 , G06F9/467 , G06F2212/251 , H04L45/74
摘要： A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).
摘要翻译：事务存储器（TM）包括控制电路管线和相关联的存储器单元。存储单元存储多个环。对于每个环，流水线保持头指针和尾指针。管道的环操作阶段将维护指针，因为值被放置在环上并被取消。如果环未满，则put命令会使TM将值放入环中。如果环不为空，则get命令使TM取环，如果环具有至少预定量的可用缓冲空间，则具有低优先级命令的put将导致TM将值放入环中。从一组ring命令获取，使TM从最高优先级非空环（指定的一组环）获取一个值。

49. 发明申请

US20140201734A1 COMPARTMENTALIZATION OF THE USER NETWORK INTERFACE TO A DEVICE 有权
标题翻译：用户网络接口对设备的分层化
公开(公告)号：US20140201734A1
公开(公告)日：2014-07-17
申请号：US13742311
申请日：2013-01-15
申请人： Jason Scott McMullan , Trevor William Patrie , Peter Liudmilov Djalaliev , Roelof Nico du Toit
发明人： Jason Scott McMullan , Trevor William Patrie , Peter Liudmilov Djalaliev , Roelof Nico du Toit
IPC分类号： G06F9/455
CPC分类号： H04L41/0806 , G06F9/455 , G06F9/45558 , G06F2009/45595 , H04L12/6418 , H04L63/0807 , H04L67/025
摘要： A device has physical network interface port through which a user can monitor and configure the device. A backend process and a virtual machine (VM) execute on a host operating system (OS). A front end user interface process executes on the VM, and is therefore compartmentalized in the VM. There is no front end user interface executing on the host OS outside the VM. The only management access channel into the device is via a first communication path through the physical network interface port, to the VM, up the VM's stack, and to the front end process. If the backend process is to be instructed to take an action, then the front end process forwards an application layer instruction to the backend process via a second communication path. The instruction passes down the VM stack, across a virtual secure network link, up the host stack, and to the backend process.
摘要翻译：设备具有物理网络接口端口，用户可以通过该端口监视和配置设备。后台进程和虚拟机（VM）在主机操作系统（OS）上执行。前端用户界面进程在VM上执行，因此在虚拟机中进行分区。在VM外部的主机操作系统上没有执行前端用户界面。设备中唯一的管理访问通道是通过物理网络接口端口，VM，VM堆栈以及前端进程的第一个通信路径。如果要指示后端进程采取行动，则前端进程通过第二通信路径将应用层指令转发到后端进程。该指令通过虚拟机堆栈，跨虚拟安全网络链接，主机堆栈以及后端进程传递。

50. 发明申请

US20130219100A1 Staggered Island Structure In An Island-Based Network Flow Processor 有权
标题翻译：基于岛屿网络流处理器的交错岛结构
公开(公告)号：US20130219100A1
公开(公告)日：2013-08-22
申请号：US13399433
申请日：2012-02-17
申请人： Gavin J. Stark
发明人： Gavin J. Stark
IPC分类号： G06F13/36
CPC分类号： G06F13/4022 , G06F13/00 , G06F13/28 , G06F17/5072 , G06F17/5077 , H04L12/54 , H04L12/56 , H04L51/00
摘要： An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. In one example, the configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit. The rectangular islands of one row are oriented in staggered relation with respect to the rectangular islands of the next row. The left and right edges of islands in a row align with left and right edges of islands two rows down in the row structure. The data bus involves multiple meshes. In each mesh, the island has a centrally located crossbar switch and six radiating half links, and half links down to functional circuitry of the island. The staggered orientation of the islands, and the structure of the half links, allows half links of adjacent islands to align with one another.
摘要翻译：基于岛屿的网络流处理器（IB-NFP）集成电路包括以行排列的矩形岛。在一个示例中，可配置的网格数据总线可配置成形成命令/推/拉数据总线，多个事务可以同时发生在集成电路的不同部分上。一行的矩形岛相对于下一行的矩形岛定向成交错关系。一行中的岛的左边缘和右边缘与行结构中两行向下的岛的左边缘和右边缘对齐。数据总线涉及多个网格。在每个网格中，岛具有位于中心的交叉开关和六个辐射半连接，并且一半连接到岛的功能电路。岛屿的交错取向和半连接的结构允许相邻岛屿的一半链接彼此对齐。

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