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    • 43. 发明专利
    • LIQUID CRYSTAL DISPLAY
    • JPH04284493A
    • 1992-10-09
    • JP29761191
    • 1991-10-18
    • MARCONI GEC LTD
    • AREN MOSURIIPATORITSUKU KORIN RANDORU
    • G02F1/133G09G3/36
    • PURPOSE: To perform the interlacing of frame lines. CONSTITUTION: When driving the liquid crystal cell of a resistance coupling transistor type active matrix drive liquid crystal display, in a first field time, the horizontal columns N-1 and N+1 of the cells are sequentially driven by adding transistor ON pulses to horizontal column driving lines 10 and 12 and reference signals are sequentially impressed to horizontal column driving lines 11 and 13 corresponding to the horizontal columns N and N+2 so as to match the ON pulses for the horizontal column N-1 and the reference signals for the horizontal column N. Then, in a second field time, the horizontal columns N and N+1 of the cells are sequentially driven by adding the transistor ON pulses to the corresponding horizontal column driving lines and the reference signals are sequentially impressed to the horizontal column driving line 12 corresponding to the horizontal columns N+1 and N+3 so as to match the ON pulses for the horizontal column N and the reference signals for the horizontal column N+1.
    • 49. 发明专利
    • RING-TYPE LOCAL AREA NETWORK
    • JPH01112847A
    • 1989-05-01
    • JP18275088
    • 1988-07-21
    • MARCONI GEC LTD
    • JIYON RATSUSERU
    • H04L12/42H04L12/43H04L12/433
    • PURPOSE: To avoid the loss of data by setting up a transmitting clock as a free-running type, avoiding the generation of a jitter between clocks having slightly different frequency band and triggering a transmitting clock generator by a fixed point in a received packet. CONSTITUTION: Each node for transmitting/receiving a packet with common length to/from a ring is provided with two shift registers, length of each shift register corresponds to one packet and the shift registers are respectively functioned as a receiving register RX and a transmitting register TX. A received clock is locked as data, i.e., data are restored from a data flow to which a clock for inputting the data to the receiving register RX at suitable timing is inputted. At a moment when the prescribed part of an input packet is received by the receiving register RX, a transmitting clock is triggered by a trigger means connected to the registe RX. Since the transmitting clock is a free- running type, a receiving clock is locked as data, and in order to avoid the loss of a certain data due to the collection of data in a node the start of a transmitting data packet is triggered by a fixed pant in a received packet.