专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明专利

DE2935199C2 未知
公开(公告)号：DE2935199C2
公开(公告)日：1987-03-12
申请号：DE2935199
申请日：1979-08-31
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： GORGENS, RICHARD A., BREDFORD, MASS., US
IPC分类号： H04L9/32 , G06Q20/10 , G06Q20/40 , G07D11/00 , G07F7/10 , G06F5/00 , G07D1/00 , G07C9/00
摘要： A banking system is provided which is comprised of a central computer, a customer accounts main memory, and plural remote transaction terminals in communication with the central computer. Each remote terminal includes a cash dispensing apparatus, a personal identification number (PIN) signal generator, a random number (RN) signal generator, a security device and a cash dispenser. The communication paths from the RN and PIN signal generators to the security device are wholly contained within the remote terminal and inaccessible to would-be thieves. The remote terminals also include data entry devices activated by a customer to provide a PIN number, a PIN OFFSET number bearing a predetermined relationship to both the PIN number and a customer information file (CIF) signal stored in main memory, and other banking information. In response to a customer-initiated operation, a remote terminal supplies bank transaction and customer identification information to the central computer. Upon receiving information from a remote terminal, the central computer searches the customer's record in main memory for a CIF number associated with the customer's account. The central computer thereafter forms a composite signal from the RN, CIF and PIN OFFSET signals which is applied to the security device of the remote terminal. The RN signal serves to conceal both the CIF and PIN OFFSET signals from an attempted interception during transmission from the central computer to the remote terminal. The security device includes a comparator for generating a DISPENSE signal when the PIN and RN signals bear a predetermined relationship to the composite signal. The cash dispenser includes a cash storage portion and a dispensing mechanism for issuing one or more cash units in response to a DISPENSE signal.

42. 发明专利

DE3018027C2 未知
公开(公告)号：DE3018027C2
公开(公告)日：1987-02-19
申请号：DE3018027
申请日：1980-05-10
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： RATHBUN, DONALD J., ANDOVER, MASS., US , CAMBELL, PETER P., NASHUA, N.H., US
IPC分类号： H03M5/12 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B27/10 , H04L25/49 , G06F12/00 , G06F13/14
摘要： Information to be written in the form of magnetic flux reversals on the surface of a disk or diskette is applied in serial fashion to a first shift registor. The parallel outputs of the shift register address a PROM. The PROM output is applied to a second shift register in the form of clock and data bits to be written on the disk or diskette magnetic surface. Control signals applied to the PROM address terminals select the mode, FM or MFM, the address mark or if precompensation is required.

43. 发明专利

DE2831684C2 未知
公开(公告)号：DE2831684C2
公开(公告)日：1987-01-15
申请号：DE2831684
申请日：1978-07-19
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： GESTON JUN., EDWARD F., LYNN, MASS., US , CASSARINO JUN., FRANK V., WESTON, MASS., US
IPC分类号： G06F11/22 , G06F11/00 , G06F11/10 , G06F11/26 , G06F11/267 , G06F11/277 , G06F13/00
摘要： A firmware/hardware method and system is provided for testing interface logic in a data processing system having a plurality of system units intercommunicating over a common electrical bus. Under firmware control, an incorrect parity is generated in a main memory address to be loaded into output registers of a system unit supplying information to the bus. A bus cycle request is issued by the system unit, and when the bus is made available the system unit acknowledges the memory address to initiate a transfer of data from the bus into the input registers of the system unit. Thereafter, the data in the output registers of the device may be compared with the data in the input registers to detect interface logic errors.

44. 发明专利

DE2400249C2 未知
公开(公告)号：DE2400249C2
公开(公告)日：1986-11-20
申请号：DE2400249
申请日：1974-01-04
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： DEVOY, DAVID D., DEDHAM, MASS., US , BARLOW, GEORGE J., TEWKSBURY, MASS., US , KLASHKA, JOHN A., ANDOVER, MASS., US
IPC分类号： G06F12/16 , A61K31/355 , G06F3/06 , G06F11/00 , G06F11/10 , G11B20/14 , G11B20/18 , G11B20/20 , H03M13/00 , G11B5/09

45. 发明专利

AU5570586A MULTIPROCESSORS ON A SINGLE SEMICONDUCTOR SHIP 未知
公开(公告)号：AU5570586A
公开(公告)日：1986-10-16
申请号：AU5570586
申请日：1986-04-07
申请人： HONEYWELL INFORMATION SYSTEMS INC
发明人： JOYCE THOMAS J , KELLY RICHARD P , SHEN JIAN-KUO , RAGUIN MICHEL M
IPC分类号： G06F15/16 , G06F9/38 , G06F15/177 , G06F13/00 , G06F7/48
摘要： A data processing system includes the functionality of a commercial instruction processor, a scientific instruction processor and a basic instruction processor integrated into a single semiconductor logic element.

46. 发明专利

DE2728275C2 未知
公开(公告)号：DE2728275C2
公开(公告)日：1986-10-09
申请号：DE2728275
申请日：1977-06-23
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： RATHBUN, DONALD J., ANDOVER, MASS., US
IPC分类号： H03M5/12 , G11B20/14 , H04L25/49 , H03M5/04 , G11B20/16
摘要： Data and clock bits are sampled by use of two delay means such as shift registers which are enabled at a clock rate which is set so that a first such delay means coupled to receive the bits includes no more than one bit therein at any time. The receipt of a bit substantially at the midway point of the second delay means, which is coupled serially to receive bits from the first delay means, causes a sampling signal to be generated in response to which a determination is made as to whether another bit has been received by the first delay means. Further logic is provided to recover the data bits.

47. 发明专利

AU4814985A PROGRAMMABLE UNIVERSAL SYNCHRONISATION BYTE DETECTOR 未知
公开(公告)号：AU4814985A
公开(公告)日：1986-04-10
申请号：AU4814985
申请日：1985-10-01
申请人： HONEYWELL INFORMATION SYSTEMS INC
发明人： GETSON EDWARD F , BRADLEY JOHN W , COTE BRUCE R
IPC分类号： G06F3/06 , G06F5/00 , G06F13/42
摘要： A programmable synchronization byte detector in a disk controller includes a shift register for serially receiving and shifting in the register a stream of bits read out from a disk unit, a processor for generating a plurality of select signals, a register for storing and making available over a time period one of the select signals, and a multiplexer receiving in input the parallel bit output of the shift register and transferring in output the select bit signal under control of the select signal received from the register. The signal in output from the multiplexer is used as synchronization signal for placing the disk controller in byte synchronization with the stream of bits received form the disk device.

48. 发明专利

AU4752285A GRAPHIC DISPLAY SCAN LINE WINDOWING CAPABILITY 未知
公开(公告)号：AU4752285A
公开(公告)日：1986-03-27
申请号：AU4752285
申请日：1985-09-17
申请人： HONEYWELL INFORMATION SYSTEMS INC
发明人： BRUCE KENNETH E
IPC分类号： G09G5/14 , G09G5/40 , G06F3/153
摘要： The invention pertains to a computer display system for displaying text and graphics on a scan line basis wherein a scan line windowing apparatus for selectively blanking the graphics display is provided.A bit map memory, in addition to storing information to be displayed on a CRT, further stores a bit for each scan line which is utilized to control the enabling or disabling of a portion of the information in the bit map memory which is to be displayed on the CRT.

49. 发明专利

DE2517302C2 未知
公开(公告)号：DE2517302C2
公开(公告)日：1985-12-12
申请号：DE2517302
申请日：1975-04-18
申请人： HONEYWELL INFORMATION SYSTEMS INC., WALTHAM, MASS., US
发明人： BARBOUR, KENNETH R., BURLINGTON, MASS., US , EVANS, HENRY J., HARVARD, MASS., US
IPC分类号： G06F13/14 , G06F12/02 , G06F9/46
摘要： A plurality of peripheral devices having physical addresses are accessed by a host processor by use of logical addresses which are utilized by the various programs in a multiprocessing environment. Input/output tables are arranged to include pointers for relating the logical address provided by a programmer to the physical address of the device thereby providing necessary device specific information to the peripheral controller coupled with the peripheral devices. The input/output tables are structured so that pointers relating the physical and logical addresses may be changed to reassign the logically addressed device to another device and accordingly to point to another physical address.

50. 发明专利

AU4284185A SINGLE REVOLUTION DISK SECTOR FORMATTER 未知
公开(公告)号：AU4284185A
公开(公告)日：1985-11-28
申请号：AU4284185
申请日：1985-05-24
申请人： HONEYWELL INFORMATION SYSTEMS INC
发明人： TARBOX BRUCE H , RATHBUN DONALD J , SU TAIAN
IPC分类号： G06F3/06 , G11B20/12
摘要： A track of a disk device is formatted on a single revolution of the disk by using a read only memory (ROM) to store control codes and a random access memory (RAM) to store address field and data field bytes. A DMA controller simultaneously addresses ROM and RAM. Control codes are read into a control first in-first out memory and data codes are read into a data first in-first out memory. The control codes are applied to a decoder whose output signals control cyclic redundancy check and error detection and correction logic as well as the data first in-first out memory. The serial output from both the data first in-first out memory and the cyclic redundancy check logic are written on disk track.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式