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31. 发明公开

EP3226433A3 DEMODULATOR OF A WIRELESS COMMUNICATION READER 审中-公开
标题翻译：无线通信阅读器的解调器
公开(公告)号：EP3226433A3
公开(公告)日：2017-10-25
申请号：EP17158554.0
申请日：2017-02-28
申请人： Intel IP Corporation
发明人： ZHU, Jie , FIEVET, Sebastien , KUTTAN, Sathish K.
IPC分类号： H04B5/00 , H04W4/00 , H03D1/00 , H03D1/02 , H03D1/22 , H04L25/06 , H03D3/00 , H03D3/06 , H03D3/18 , H04L27/06 , H03K9/02 , H04L27/233
CPC分类号： H04B5/02 , H03D1/2209 , H03D1/2245 , H04B5/0031 , H04L25/06 , H04L27/06 , H04L27/2335 , H04W4/80
摘要： A demodulator including a peak sampler to control an ADC or a digital resampler to sample a carrier signal in an unmodulated state at peaks, and to sample the carrier signal in a modulated state at a phase of the unmodulated state; and an envelope builder to determine an envelope signal based on differentials between maximum and minimum peaks of respective cycles of the sampled carrier signal. Further, a demodulator having an offset estimator to estimate in-phase and quadrature components of a carrier signal in an unmodulated state to determine in-phase and quadrature component offsets; a load modulated signal estimator to estimate in-phase and quadrature components of a load modulated signal by removing the in-phase and quadrature component offsets from in-phase and quadrature component samples of the carrier signal; and an envelope builder to build an envelope signal by combining the in-phase and quadrature components of the load modulated signal.
摘要翻译：一种解调器，包括：峰值采样器，用于控制ADC或数字重采样器在峰值处对未调制状态的载波信号进行采样;以及在未调制状态的相位处以调制状态对载波信号进行采样; 以及包络建立器，用于基于采样的载波信号的各个周期的最大和最小峰值之间的差来确定包络信号。此外，解调器具有偏移估计器，用于估计处于未调制状态的载波信号的同相和正交分量，以确定同相和正交分量偏移; 负载调制信号估计器，用于通过从载波信号的同相和正交分量采样中去除同相和正交分量偏移来估计负载调制信号的同相和正交分量; 以及包络生成器，用于通过组合负载调制信号的同相和正交分量来构建包络信号。

32. 发明授权

EP1116323B1 LOCK-IN AID FREQUENCY DETECTOR 有权
标题翻译：频率检测器FOR LOCKING
公开(公告)号：EP1116323B1
公开(公告)日：2006-12-27
申请号：EP99946679.0
申请日：1999-08-25
申请人： MAXIM INTEGRATED PRODUCTS, INC. , Hisys GmbH
发明人： FILIP, Jan
IPC分类号： H03D3/24 , H03D3/18 , H03D3/00 , H03D3/02 , H03D1/00
CPC分类号： H03L7/087 , H03D13/003 , H03L7/095 , H03L7/10
摘要： Circuit and method for generating a signal for use in locking a second signal on a first signal. The first and second signals have an associated frequency. A first beat note signal (PD1) and a second beat note signal (PD2) are generated from the first and second signals, respectively, when the frequencies of the first and second signals are not equal. The circuit includes a first and second flip-flop and detector circuitry. The first flip-flop (502) is configured to receive the first and second beat note signals for generating a first state signal (S0). The first flip-flop (502) generates the first state signal (S0) by sampling the second beat note signal (PD1) at a first periodic interval of the first beat note signal. The second flip-flop (504) is configured to receive the first and second beat note signals for generating a second state signal (S1). The second flip-flop (504) generates the second state signal (S1) by sampling the second beat note signal at a second periodic interval of the first beat note signal (PD1). The detector circuitry (506, 508) is coupled to receive the first and second state signals from the first and second flip-flops for detecting a polarity of the frequency difference between the first and second signals. The polarity of the frequency difference is defined in a tri-state having a positive state, a negative state, and a zero state.

33. 发明公开

EP1116323A4 LOCK-IN AID FREQUENCY DETECTOR 有权
标题翻译：频率检测器FOR LOCKING
公开(公告)号：EP1116323A4
公开(公告)日：2004-09-29
申请号：EP99946679
申请日：1999-08-25
申请人： MAXIM INTEGRATED PRODUCTS , HISYS GMBH
发明人： FILIP JAN
IPC分类号： H03D13/00 , H03L7/087 , H03L7/095 , H03L7/10 , H04L7/033 , H03D3/24 , H03D1/00 , H03D3/00 , H03D3/02 , H03D3/18
CPC分类号： H03L7/087 , H03D13/003 , H03L7/095 , H03L7/10
摘要： Circuit and method for generating a signal for use in locking a second signal on a first signal. The first and second signals have an associated frequency. A first beat note signal (PD1) and a second beat note signal (PD2) are generated from the first and second signals, respectively, when the frequencies of the first and second signals are not equal. The circuit includes a first and second flip-flop and detector circuitry. The first flip-flop (502) is configured to receive the first and second beat note signals for generating a first state signal (S0). The first flip-flop (502) generates the first state signal (S0) by sampling the second beat note signal (PD1) at a first periodic interval of the first beat note signal. The second flip-flop (504) is configured to receive the first and second beat note signals for generating a second state signal (S1). The second flip-flop (504) generates the second state signal (S1) by sampling the second beat note signal at a second periodic interval of the first beat note signal (PD1). The detector circuitry (506, 508) is coupled to receive the first and second state signals from the first and second flip-flops for detecting a polarity of the frequency difference between the first and second signals. The polarity of the frequency difference is defined in a tri-state having a positive state, a negative state, and a zero state.

34. 发明授权

EP0040272B1 A demodulator system including a tunable discriminator suitable for use in a Secam television receiver 失效
标题翻译：一种包括可用于SECAM电视接收器的可调节分辨率的解调器系统
公开(公告)号：EP0040272B1
公开(公告)日：1984-08-22
申请号：EP80301666.6
申请日：1980-05-20
申请人： MOTOROLA, INC.
发明人： Gay, Michael John , Gutmann, Johannes A.
IPC分类号： H04N9/50 , H03D3/18
CPC分类号： H04N11/186

35. 发明公开

EP0072848A4 BIPHASE DETECTOR. 失效
标题翻译： ZWEIPHASENDETEKTOR。
公开(公告)号：EP0072848A4
公开(公告)日：1983-07-04
申请号：EP82900876
申请日：1982-02-04
申请人： SPERRY CORP
发明人： MAINE REUBEN E
IPC分类号： H04L27/22 , H04L25/49 , H04L27/227 , H03D3/18 , H03K9/00
CPC分类号： H04L25/4904 , H04L27/2272

36. 发明公开

EP0040272A1 A demodulator system including a tunable discriminator suitable for use in a Secam television receiver 失效
标题翻译： Demodulatorsystem mit einstellbarem Frequenzdiskriminator zur Verwendung in einem SECAM-Fernsehempfänger。
公开(公告)号：EP0040272A1
公开(公告)日：1981-11-25
申请号：EP80301666.6
申请日：1980-05-20
申请人： MOTOROLA, INC.
发明人： Gay, Michael John , Gutmann, Johannes A.
IPC分类号： H04N9/50 , H03D3/18
CPC分类号： H04N11/186
摘要： A demodulating system to be utilized in Secam television receivers for deriving the R-Y and B-Y chrominance information signals from the frequency modulated Secam RF subcarrier frequencies without the necessity for precise and stable tuned circuits. The demodulating system includes a single discriminator (66) having an electronically tunable center frequency, a remodulator (42), for producing a reference frequency amplitude modulated by the chrominance information signals which are supplied to a commutator as known, and a feedback circuit coupled between the discriminator and remodulator. The discriminator is selectively tuned to a reference center frequency during each picture line clamp period to produce a zero level output signal. During the chrominance information portion of each line, the center frequency of the discriminator is alternately offset by first and second control signals to center frequencies coinciding with the two reference frequencies to produce a zero output level whenever the Secam signals are atthe respective RF subcarrier frequencies. The feedback circuit ensures that the zero output levels obtained during the information carrying portion of each line is identical with the zero output level set during the clamp period.
摘要翻译：一种用于Secam电视接收机的解调系统，用于从频率调制的Secam RF子载波频率导出R-Y和B-Y色度信息信号，而不需要精确和稳定的调谐电路。解调系统包括具有电子可调谐中心频率的单鉴别器（66），再调制器（42），用于产生由已知的提供给换向器的色度信息信号调制的参考频率幅度，以及耦合在鉴别器和再调制器。在每个图像线钳位周期期间，鉴别器被选择性地调谐到参考中心频率以产生零电平输出信号。在每条线的色度信息部分期间，只要Secam信号处于相应的RF子载波频率，鉴别器的中心频率被第一和第二控制信号交替地偏移到与两个参考频率重合的中心频率，以产生零输出电平。反馈电路确保在每条线路的信息传送部分期间获得的零输出电平与在钳位期间设定的零输出电平相同。

37. 发明公开

EP1543631A4 VARIABLE-LENGTH CORRELATOR FOR SPREAD-SPECTRUM COMMUNICATIONS 审中-公开
标题翻译： CORRELATOR变量LUNG扩频
公开(公告)号：EP1543631A4
公开(公告)日：2011-07-27
申请号：EP03759304
申请日：2003-09-18
申请人： THOMSON LICENSING
发明人： LITWIN JR LOUIS ROBERT
IPC分类号： H04B1/707 , H04L27/00 , H04B1/69 , H03D3/18 , H03D3/24 , H04L7/00 , H04L25/49 , H04L27/06
CPC分类号： H04B1/7075 , H04B1/7087 , H04B1/709 , H04L2027/003 , H04L2027/0081

38. 发明公开

EP1671417A1 RECEIVER INCLUDING AN OSCILLATION CIRCUIT FOR GENERATING AN IMAGE REJECTION CALIBRATION TONE 有权
标题翻译：具有用于产生图像排斥甲振荡电路RECEIVER KALIBRATIONSTONS
公开(公告)号：EP1671417A1
公开(公告)日：2006-06-21
申请号：EP04785214.0
申请日：2004-09-29
申请人： Silicon Laboratories, Inc.
发明人： WILLINGHAM, Scott, D.
IPC分类号： H03D3/18 , H04B1/30
CPC分类号： H04B1/30 , H04B17/21
摘要： A receiver circuit includes an oscillator circuit (100) configured to generate a calibration tone (75) and a phase locked loop (PLL) reference signal (72). An output frequency of the VCO (172) may be divided by respective amounts to derive a desired calibration tone frequency and a desired PLL reference signal frequency. In addition to the oscillator circuit, the receiver circuit may further include a phase locked circuit (60) configured to generate a PLL output signal (61) that is phase locked in relation to the PLL reference signal (72). During a calibration mode, a quadrature generator (26) may be used to generate quadrature mixer local oscillator signals dependent upon the PLL output signal (61), and an in-phase/quadrature mixer (25) may be used to mix the calibration tone (65) with the quadrature mixer LO signals.

39. 发明公开

EP1116323A1 LOCK-IN AID FREQUENCY DETECTOR 有权
标题翻译：频率检测器FOR LOCKING
公开(公告)号：EP1116323A1
公开(公告)日：2001-07-18
申请号：EP99946679.0
申请日：1999-08-25
申请人： MAXIM INTEGRATED PRODUCTS , Hisys GmbH
发明人： FILIP, Jan
IPC分类号： H03D3/24 , H03D3/18 , H03D3/00 , H03D3/02 , H03D1/00
CPC分类号： H03L7/087 , H03D13/003 , H03L7/095 , H03L7/10
摘要： Circuit and method for generating a signal for use in locking a second signal on a first signal. The first and second signals have an associated frequency. A first beat note signal (PD1) and a second beat note signal (PD2) are generated from the first and second signals, respectively, when the frequencies of the first and second signals are not equal. The circuit includes a first and second flip-flop and detector circuitry. The first flip-flop (502) is configured to receive the first and second beat note signals for generating a first state signal (S0). The first flip-flop (502) generates the first state signal (S0) by sampling the second beat note signal (PD1) at a first periodic interval of the first beat note signal. The second flip-flop (504) is configured to receive the first and second beat note signals for generating a second state signal (S1). The second flip-flop (504) generates the second state signal (S1) by sampling the second beat note signal at a second periodic interval of the first beat note signal (PD1). The detector circuitry (506, 508) is coupled to receive the first and second state signals from the first and second flip-flops for detecting a polarity of the frequency difference between the first and second signals. The polarity of the frequency difference is defined in a tri-state having a positive state, a negative state, and a zero state.

40. 发明公开

EP0488558A1 Quadrature detecting apparatus 失效
标题翻译： DetektorfürQuadraturfrequenz-Modulationssignal。
公开(公告)号：EP0488558A1
公开(公告)日：1992-06-03
申请号：EP91310582.1
申请日：1991-11-15
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Ikeda, Masaharu
IPC分类号： H03D3/18
CPC分类号： H03D3/18
摘要： A quadrature detecting apparatus is provided which is intended to prevent a demodulated output from being influenced by fluctuations in amplitudes of signals generated from angle-modulated signal sources such as a phase-modulated signal and a frequency-modulated signal, even if the amplitude of a driving voltage applied to a connection between the bases of a pair of transistors constituting a phase detecting device is made larger in order to enhance the demodulation sensitivity and reduce noises produced during demodulation. As an example of a resolution, the quadrature detecting apparatus comprises two coupling devices (D, E), two current dividing devices (F, G) coupled to generate a phase detecting output, a current dividing device (H, I) coupled to generate a re-mixed output, and a phase detecting device, wherein the outputs of the two coupling devices are connected to the two current driving devices driven by the same signal, so that the respective input and output terminals are at the same voltage level, whereby two outputs thereof are not influenced by fluctuations in amplitudes of angle-modulated signals supplied to the coupling devices.
摘要翻译：提供一种正交检测装置，其旨在防止解调输出受角度调制信号源（例如相位调制信号和调频信号）产生的信号幅度的波动的影响，即使是构成相位检测装置的一对晶体管的基极之间的连接施加的驱动电压变大，以提高解调灵敏度并减少解调时产生的噪声。作为分辨率的例子，正交检测装置包括两个耦合装置（D，E），耦合以产生相位检测输出的两个电流分配装置（F，G），耦合以产生相位检测输出的电流分配装置（H，I）再混合输出和相位检测装置，其中两个耦合装置的输出连接到由相同信号驱动的两个电流驱动装置，使得相应的输入和输出端子处于相同的电压电平，由此其两个输出不受供给到耦合装置的角度调制信号的振幅的波动的影响。

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