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31. 发明授权

US4384328A Programmable calculator including magnetic reading and recording means 失效
标题翻译：可编程计算器，包括磁读和记录装置
公开(公告)号：US4384328A
公开(公告)日：1983-05-17
申请号：US239867
申请日：1981-03-02
申请人： Robert E. Watson , Jack M. Walden , Charles W. Near
发明人： Robert E. Watson , Jack M. Walden , Charles W. Near
IPC分类号： G06F15/02 , G06F3/02 , G06F3/06 , G06F3/14 , G06F13/08
CPC分类号： G07G1/14 , G06F15/0233
摘要： A modular read-write and read-only memory unit capable of employing both direct and indirect decimal and symbolic addressing, a central processing unit capable of performing both serial binary and parallel binary-coded-decimal direct and indirect memory register arithmetic, and an input-output control unit capable of bidirectionally transferring information between the central processing unit and a number of input and output units are controlled by a microprocessor included in the central processing unit. The input and output units include a keyboard input unit, a magnetic card reading and recording unit capable of bidirectionally transferring information between an external magnetic card and the read-write memory unit, and a solid state output display unit capable of displaying three lines of numeric information. The memory, central processing, input-output control, input, and output units are employed to provide an adaptable programmable calculator that may be operated manually by the user from the keyboard input unit or automatically by a program stored in the read-write memory unit. The calculator may also be employed to load programs into the read-write memory unit from the keyboard input unit, to separately transfer either data or programs bidirectionally between the read-write memory unit and an external magnetic card, and to code programs stored in the read-write memory unit as being secure when they are transferred to an external magnetic card, thereby preventing users of the calculator from re-transferring them to an external magnetic card or obtaining any indication of the individual program steps once they are reloaded into the calculator.
摘要翻译：一种能够采用直接和间接十进制和符号寻址的模块化读写和只读存储器单元，能够执行串行二进制和并行二进制编码十进制直接和间接存储器寄存器运算的中央处理单元和输入 - 能够在中央处理单元和多个输入和输出单元之间双向传送信息的输出控制单元由包括在中央处理单元中的微处理器控制。输入和输出单元包括能够在外部磁卡和读写存储器单元之间双向传送信息的键盘输入单元，磁卡读取和记录单元以及能够显示三行数字的固态输出显示单元信息。存储器，中央处理，输入输出控制，输入和输出单元用于提供可由用户从键盘输入单元手动操作或由存储在读写存储器单元中的程序自动操作的适应性可编程计算器。还可以使用计算器将程序从键盘输入单元加载到读写存储器单元中，以便在读写存储器单元和外部磁卡之间双向单独地传送数据或程序，并对存储在读写存储器单元中的程序进行编码读写存储器单元在被传送到外部磁卡时是安全的，从而防止计算器的用户重新传送到外部磁卡，或者一旦重新加载到计算器中就获得各个程序步骤的任何指示。

32. 发明授权

US4161788A Bubble memory controller with multipage data handling 失效
标题翻译：具有多页数据处理的气泡存储控制器
公开(公告)号：US4161788A
公开(公告)日：1979-07-17
申请号：US789390
申请日：1977-04-21
申请人： Robert J. Rosenblum
发明人： Robert J. Rosenblum
IPC分类号： G11C11/14 , G06F3/00 , G06F3/08 , G11C19/08 , G06F13/08 , G11C11/02
CPC分类号： G06F3/007 , G11C19/0875
摘要： A magnetic bubble memory system controller is provided to interface a user system and a magnetic domain chip. The controller will functionally accept commands from a user system and deliver those same commands to the appropriate devices associated with the magnetic bubble memory. A further function of the controller device will be to enable multipage read and write functions within the major loop of a magnetic bubble memory chip organization.
摘要翻译：提供磁性气泡存储器系统控制器来接口用户系统和磁畴芯片。控制器将在功能上接受来自用户系统的命令，并将相同的命令传递到与磁性气泡存储器相关联的适当设备。控制器设备的另一个功能将是在磁性气泡存储器芯片组织的主循环内实现多页读取和写入功能。

33. 发明授权

US4073005A Multi-processor computer system 失效
标题翻译：多处理器计算机系统
公开(公告)号：US4073005A
公开(公告)日：1978-02-07
申请号：US435356
申请日：1974-01-21
申请人： Thomas R. Parkin
发明人： Thomas R. Parkin
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50 , G06F12/00 , G06F12/02 , G06F12/06 , G06F9/18 , G06F9/16 , G06F13/08
CPC分类号： G06F9/4881
摘要： Two or more processors share a large main memory in which are stored the programs and data sets on which the processors operate. Each processor operates independently from every other one, and selects its tasks for operation on the basis of information contained in tables which may be updated independently by each processor.
摘要翻译：两个或多个处理器共享一个大的主存储器，其中存储处理器所处的程序和数据集。每个处理器独立于其他处理器操作，并且基于可由每个处理器独立更新的表中包含的信息来选择其操作任务。

34. 发明授权

US3465297A Program protection arrangement 失效
标题翻译：程序保护安排
公开(公告)号：US3465297A
公开(公告)日：1969-09-02
申请号：US3465297D
申请日：1966-09-30
申请人： CONTROL DATA CORP
发明人： THOMAS NEIL L , PETRINI ALBERT A
IPC分类号： G06F12/14 , G06F13/24 , G06F13/08
CPC分类号： G06F13/24 , G06F12/1491

35. 发明专利

CS230633B1 DISC STORE CONTROLLER CONNECTION 未知
公开(公告)号：CS230633B1
公开(公告)日：1984-08-13
申请号：CS252283
申请日：1983-04-08
申请人： LOUTOCKY DUSAN , KUBIN PAVEL
发明人： LOUTOCKY DUSAN , KUBIN PAVEL
IPC分类号： G06F13/00 , G06F13/08

36. 发明专利

ES514050A0 未知
公开(公告)号：ES514050A0
公开(公告)日：1983-04-01
申请号：ES514050
申请日：1982-07-16
申请人： RCA CORP
IPC分类号： H03M7/02 , G06F1/03 , G06F5/00 , H04N5/14 , H04N7/12 , G06F13/08
摘要： A digital signal processor uses a RAM for signal processing. This allows the transfer function to be easily changed by either hardwired circuitry or a microprocessor. Two RAMs per channel can be used, one processing the signal, while the other has its transfer function changed. The operations of the RAMs can be changed during a portion of the input signal, e.g. blanking times, when the switch over is not objectionable.

37. 发明专利

CS220050B1 CONNECTION OF THE ADAPTOR FOR THE CONTROL OF THE DISC MEMORY ACTION 未知
公开(公告)号：CS220050B1
公开(公告)日：1983-03-25
申请号：CS9082
申请日：1982-01-05
申请人： LOUTOCKY DUSAN , KUBIN PAVEL
发明人： LOUTOCKY DUSAN , KUBIN PAVEL
IPC分类号： G06F13/00 , G06F13/08

38. 发明专利

CS207100B1 CONNECTION FOR CONNECTING THE CASETTE TAPE MEMORY TO THE MICROCOMPUTER 未知
公开(公告)号：CS207100B1
公开(公告)日：1981-07-31
申请号：CS851379
申请日：1979-12-06
申请人： JANU KAREL , NEMEC DALIBOR
发明人： JANU KAREL , NEMEC DALIBOR
IPC分类号： G06F7/24 , G06F13/08

39. 发明专利

BR7906736A 未知
公开(公告)号：BR7906736A
公开(公告)日：1980-06-17
申请号：BR7906736
申请日：1979-10-18
申请人： IBM
发明人： HAMMER W , LEWIS D
IPC分类号： G06F12/10 , G06F12/08 , G06F13/08

40. 发明专利

FR2434431A1 未知
公开(公告)号：FR2434431A1
公开(公告)日：1980-03-21
申请号：FR7917083
申请日：1979-06-29
申请人： BUNKER RAMO
IPC分类号： G06F3/06 , G06F12/08 , G06F12/12 , G06F13/08 , G11C9/00
摘要： A programmable control unit for disk memory and controller comprising a microprocessor (MPU), random access memory (RAM) used as a buffer to cache disk resident data used by a data processing system (DPS), and a configurable data path (CDP) which couples the DPS to the disk controller. The (MPU) is programmed to provide the DPS rapid access to disk resident data by so controlling the CDP as to maintain a memory cache of disk resident data in the RAM. Data is cached under either directed control via an application level task or operator console directive, or under dynamic control through which a predetermined number of successive blocks of data are read from the disk and stored in the RAM each time any one block is addressed, and once the RAM is full, by discarding from the RAM a block of data which the immediate history has shown is least useful.

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