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    • 32. 发明申请
    • Ultraviolet erasable semiconductor memory device
    • 紫外线可擦除半导体存储器件
    • US20050232026A1
    • 2005-10-20
    • US11053851
    • 2005-02-10
    • Yukihisa Kumagai
    • Yukihisa Kumagai
    • G11C16/04G11C5/00G11C8/00G11C11/34G11C11/42G11C16/00G11C16/06G11C16/18H01L21/8247H01L27/10H01L27/115H01L29/78H01L29/788H01L29/792
    • G11C16/18G11C8/00
    • Each memory cell of an EPROM contains two MOSFETs and a data of each memory cell is read out by detecting a current difference between the two MOSFETs by using a differential amplifier. In such constitution as described above, even when the data is erased by irradiating an ultraviolet ray, a stable output of the differential amplifier can be obtained and, therefore, confirmation of an initialized state can be facilitated. Specifically, a channel width WA of one of the two MOSFETs constituting the memory cell is formed narrower than a channel width WB of the other. By such arrangement as described above, in an initialized state in which the ultraviolet ray is irradiated, a data signal current value IHA of the MOSFET having the channel width WA becomes smaller than a data signal current value IHB flowing in the MOSFET having the channel width WB. Accordingly, the output of the differential amplifier is fixed in accordance with a current magnitude relation of IHA
    • EPROM的每个存储单元包含两个MOSFET,并且通过使用差分放大器检测两个MOSFET之间的电流差来读出每个存储单元的数据。 在这样构成的情况下,即使通过照射紫外线来擦除数据,也能够获得稳定的差分放大器的输出,因此能够促进初始化状态的确认。 具体地,构成存储单元的两个MOSFET之一的沟道宽度W A A A形成得窄于另一个的沟道宽度W B B。 通过如上所述的布置,在照射紫外线的初始化状态下,具有沟道宽度W A A的MOSFET的数据信号电流值I H HA < 小于在具有沟道宽度W B的MOSFET中流动的数据信号电流值I HB。 因此,差分放大器的输出根据I H B H I H B B的电流大小关系固定,从而定义数据“0”。 另一方面,在写入数据“1”时,将电荷注入具有沟道宽度W B B的MOSFET的浮置栅电极以提高阈值电压Vt,然后,MOSFET为 设置为“关闭”状态。
    • 33. 发明申请
    • Method and apparatus for detecting exposure of a semiconductor circuit to ultra-violet light
    • 用于检测半导体电路对紫外光的曝光的方法和装置
    • US20040174749A1
    • 2004-09-09
    • US10378414
    • 2003-03-03
    • Shane C. Hollmer
    • G11C011/34
    • G11C16/18G11C16/22
    • A method and apparatus are disclosed for detecting if a semiconductor circuit has been exposed to ultra-violet light. An ultra-violet light detection circuit detects exposure to ultra-violet light and will automatically activate a security violation signal. The security violation signal may optionally initiate a routine to clear sensitive data from memory or prevent the semiconductor circuit from further operation. The ultra-violet light detection circuit detects whether a semiconductor circuit has been exposed to ultra-violet light, for example, by employing a dedicated mini-array of non-volatile memory cells. At least two active bit lines, blprg and bler, are employed corresponding to program and erase, respectively. One of the bit lines is only programmable and the other bit line is only eraseable. Generally, all of the bits in the dedicated non-volatile memory array are initially in approximately the same state, which could be erased, programmed or somewhere in between. An offset current is added to one bit line and a change in the resulting current difference is used to detect an exposure to ultra-violet light.
    • 公开了一种用于检测半导体电路是否已经暴露于紫外光的方法和装置。 紫外光检测电路检测到紫外光的曝光,并自动激活安全违规信号。 安全违规信号可以可选地启动例程以从存储器清除敏感数据或防止半导体电路进一步操作。 紫外光检测电路例如通过采用非易失性存储单元的专用微型阵列来检测半导体电路是否已经暴露于紫外光。 对应于编程和擦除分别使用至少两个有效位线blprg和bler。 其中一个位线只能编程,另一个位线只能擦除。 通常,专用非易失性存储器阵列中的所有位最初处于大致相同的状态,这可能被擦除,编程或其间的某处。 偏移电流被添加到一个位线,并且所得到的电流差的变化用于检测对紫外光的曝光。
    • 34. 发明申请
    • Laser programmable electrically readable phase-change memory method and device
    • 激光可编程电可读相变存储器的方法和装置
    • US20040037106A1
    • 2004-02-26
    • US10223975
    • 2002-08-20
    • MACRONIX INTERNATIONAL CO., LTD.
    • Chih-Yuan LuYi-Chou Chen
    • G11C017/14
    • G11C13/0004G11C13/04G11C16/18G11C2213/72
    • Roughly described, a phase-change memory such as a chalcogenide-based memory is programmed optically and read electrically. No complex electrical circuits are required for programming the cells. On the other hand, this memory can be read by electrical circuitry directly. The read out speed is much faster than for optical disks, and integrated circuit chips made this way are more compatible with other electrical circuits than are optical disks. Thus memories according to the invention can have simple, low power-consuming, electrical circuits, and do not require slow and power-hungry disk drives for reading. The invention therefore provides a unique low power, fast read/write memory with simple electrical circuits.
    • 粗略地描述,诸如基于硫族化物的存储器之类的相变存储器被光学地编程并且被电读取。 编程电池不需要复杂的电路。 另一方面,该存储器可以直接由电路读取。 读出速度比光盘快得多,而采用这种方式制成的集成电路芯片与其他电路比光盘更为兼容。 因此,根据本发明的存储器可以具有简单的,低功耗的电路,并且不需要用于读取的缓慢且耗电的磁盘驱动器。 因此,本发明提供了具有简单电路的独特的低功率,快速读/写存储器。
    • 36. 发明授权
    • Sealed semiconductor chip and process for fabricating sealed
semiconductor chip
    • 密封半导体芯片和制造密封半导体芯片的工艺
    • US5856705A
    • 1999-01-05
    • US734445
    • 1996-10-17
    • Chiu H. Ting
    • Chiu H. Ting
    • G11C16/18H01L23/00H01L23/29H01L23/31H01L21/78H01L29/34
    • H01L23/564G11C16/18H01L23/291H01L23/3171H01L2924/0002
    • Described is a structure and process for forming a hermetically sealed chip. This hermetically sealed chip will greatly simplify packaging requirements and eventually lead to the realization of a "packageless chip". The hermetic sealing is composed of two parts, an extremely thin passivation layer which is deposited over the entire chip top and side surfaces and a passivation layer which is deposited over the bonding pad surface. Preferably, SiN is deposited as a chip surface passivation layer and Ni is selectively deposited as a metal passivation layer. The extremely thin nitride layer will minimize the stress and the amount of hydrogen in the SiN film and minimize deleterious effects upon device performance caused by stress and hydrogen. The thickness of the metal passivation layer may be the same as that of the dielectric layer so as to give a planar surface or it may be thick enough so as to give a protruding metal passivation bump.
    • 描述了形成密封芯片的结构和工艺。 这种密封芯片将大大简化封装要求,最终导致实现“无封装芯片”。 气密密封由两部分组成,其沉积在整个芯片顶部和侧表面上的极薄的钝化层和沉积在焊盘表面上的钝化层。 优选地,SiN作为芯片表面钝化层沉积,并且Ni被选择性地沉积为金属钝化层。 极薄的氮化物层将使SiN膜中的应力和氢的量最小化,并使由应力和氢引起的对器件性能的有害影响最小化。 金属钝化层的厚度可以与电介质层的厚度相同,以便得到平坦的表面,或者可以足够厚以便产生突出的金属钝化凸块。
    • 37. 发明授权
    • Process for fabricating sealed semiconductor chip using silicon nitride
passivation film
    • 使用氮化硅钝化膜制造密封半导体芯片的工艺
    • US5300461A
    • 1994-04-05
    • US8469
    • 1993-01-25
    • Chiu H. Ting
    • Chiu H. Ting
    • G11C16/18H01L23/00H01L23/29H01L23/31H01L21/80
    • H01L23/564G11C16/18H01L23/291H01L23/3171H01L2924/0002
    • Described is a structure and process for forming a hermetically sealed chip. This hermetically sealed chip will greatly simplify packaging requirements and eventually lead to the realization of a "packageless chip". The hermetic sealing is composed of two parts, an extremely thin passivation layer which is deposited over the entire chip top and side surfaces and a passivation layer which is deposited over the bonding pad surface. Preferably, SiN is deposited as a chip surface passivation layer and Ni is selectively deposited as a metal passivation layer. The extremely thin nitride layer will minimize the stress and the amount of hydrogen in the SiN film and minimize deleterious effects upon device performance caused by stress and hydrogen. The thickness of the metal passivation layer may be the same as that of the dielectric layer so as to give a planar surface or it may be thick enough so as to give a protruding metal passivation bump.
    • 描述了形成密封芯片的结构和工艺。 这种密封芯片将大大简化封装要求,最终导致实现“无封装芯片”。 气密密封由两部分组成,其沉积在整个芯片顶部和侧表面上的极薄的钝化层和沉积在焊盘表面上的钝化层。 优选地,SiN作为芯片表面钝化层沉积,并且Ni被选择性地沉积为金属钝化层。 极薄的氮化物层将使SiN膜中的应力和氢的量最小化,并使由应力和氢引起的对器件性能的有害影响最小化。 金属钝化层的厚度可以与电介质层的厚度相同,以便得到平坦的表面,或者可以足够厚以便产生突出的金属钝化凸块。
    • 39. 发明授权
    • Method for making a ceramic lid for hermetic sealing of an EPROM circuit
    • 制造用于EPROM电路气密密封的陶瓷盖的方法
    • US5043004A
    • 1991-08-27
    • US574668
    • 1990-08-29
    • Nobuaki Miyauchi
    • Nobuaki Miyauchi
    • C04B37/04G11C16/18
    • G11C16/18
    • An assembly structure and a method for making a ceramic lid for a hermetically sealed package for an EPROM circuit are disclosed. The assembly structure includes, in combination, a ceramic lid, a UV transparent lens, and two fixtures for supporting the lens in the lid. The two fixtures are configured to contact the lens only at predetermined areas which are not crucial to UV transparency. The UV transparent lens is hermetically sealed to the ceramic lid by firing the assembly structure. The assembly structure prevents the lens from attracting foreign particulate matter during firing, thereby leaving the surfaces of the lens clean. The method provides a ceramic lid having a UV transparent lens hermetically sealed thereto, which finds wide use in integrated circuit packages for high-density EPROM's because of the untainted surfaces of the lens.
    • 公开了一种用于制造用于EPROM电路的气密封装的陶瓷盖的组装结构和方法。 组合结构包括陶瓷盖,UV透明透镜和用于将透镜支撑在盖中的两个固定装置。 两个固定装置被配置成仅在对UV透明度至关重要的预定区域接触透镜。 UV透明透镜通过烧结组装结构而密封在陶瓷盖上。 组装结构防止了镜头在烧制过程中吸引外来颗粒物,从而使透镜的表面清洁。 该方法提供了一种具有密封在其上的UV透明透镜的陶瓷盖,其由于透镜的未被保持的表面而被广泛用于高密度EPROM的集成电路封装中。