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    • 31. 发明授权
    • Sparse byte enable indicator for high speed memory access arbitration method and apparatus
    • 稀疏字节使能指示灯用于高速存储器存取仲裁方法和装置
    • US06799293B2
    • 2004-09-28
    • US09884270
    • 2001-06-19
    • Michael J. PetersJames R. Klobcar
    • Michael J. PetersJames R. Klobcar
    • G11C2900
    • G06F13/161G06F11/1076G06F2211/1066G06F2211/109
    • A sparse byte enable indicator for high speed memory access arbitration and a memory controller utilizing same is provided. According to the invention, a sparse byte enable indication is provided to the memory controller with or at about the same time that a request for a write to memory is received from a client. In response to receiving the sparse byte enable indication, the memory controller can begin to initiate a read-modify-write sequence. The present invention allows write operations involving less than complete data words in a first block of data to be completed in fewer clock cycles than in connection with controllers that do not utilize a sparse byte enable indication. The present invention is applicable in connection with any device controlling access to memory in systems utilizing error correction code.
    • 提供用于高速存储器访问仲裁的稀疏字节使能指示符和使用它的存储器控​​制器。 根据本发明,在存储器控制器中提供稀疏字节使能指示,或者在从客户端接收对存储器的写入请求的同时提供。 响应于接收到稀疏字节使能指示,存储器控制器可以开始发起读 - 修改 - 写入序列。 本发明允许在比不结合不使用稀疏字节使能指示的控制器更少的时钟周期内完成涉及少于完整的数据字的写操作。 本发明可应用于利用纠错码的系统中控制对存储器的访问的设备。
    • 33. 发明授权
    • Raid XOR operations to synchronous DRAM using a read buffer and pipelining of synchronous DRAM burst read data
    • 使用读缓冲器和流水线同步DRAM突发读数据对同步DRAM进行RAID XOR操作
    • US06370611B1
    • 2002-04-09
    • US09542624
    • 2000-04-04
    • Ryan A. CallisonWilliam C. GallowayChristopher GarzaAlbert H. Chang
    • Ryan A. CallisonWilliam C. GallowayChristopher GarzaAlbert H. Chang
    • G06F1216
    • G06F11/108G06F13/1673G06F2211/1054G06F2211/1066
    • A memory interface controller includes a read buffer to pipeline data from a synchronous dynamic random access memory (DRAM) in response to a plurality of consecutive SDRAM burst read requests, a write buffer to store write data, an exclusive or (XOR) engine to XOR the write data with the data from the read buffer, and a write interface to write resulting data from XORing the write data and the data from the read buffer to the synchronous DRAM. Data is pipelined in the read buffer by repeatedly issuing an SDRAM burst read request before data is transferred out of the synchronous DRAM in response to a previous SDRAM burst read request until a desired amount of data is stored in the read buffer. The memory interface controller thus can perform an external read-modify-write cycle for the synchronous DRAM. The synchronous DRAM can serve as a RAID (Redundant Array s of Inexpensive Disks) memory.
    • 存储器接口控制器包括响应于多个连续的SDRAM突发读取请求的来自同步动态随机存取存储器(DRAM)的流水线数据的读取缓冲器,用于存储写入数据的写入缓冲器,将异或(XOR)引擎转换为XOR 写数据与来自读缓冲器的数据,以及写接口,用于将写数据和从读缓冲器的数据进行异或写入到同步DRAM。 数据在读取缓冲器中被流水线化,通过在将数据从先前的SDRAM突发读取请求传送到同步DRAM之前重复发出SDRAM突发读取请求,直到期望的数据量被存储在读取缓冲器中为止。 因此,存储器接口控制器可以为同步DRAM执行外部读 - 修改 - 写周期。 同步DRAM可以用作RAID(廉价磁盘冗余阵列)内存。
    • 36. 发明授权
    • Data replication method over a limited bandwidth network by mirroring parities
    • 通过镜像奇偶校验在有限带宽网络上的数据复制方法
    • US07457980B2
    • 2008-11-25
    • US11017436
    • 2004-12-20
    • Ken Qing YangJohn Di Pippo
    • Ken Qing YangJohn Di Pippo
    • G06F11/00
    • G06F11/2074G06F11/1076G06F11/1451G06F11/1464G06F11/2066G06F2211/1009G06F2211/1045G06F2211/1066
    • A method dramatically reduces the amount of data to be stored and transferred in a networked storage system. Preferably, the network storage system provides continued data protection through mirroring/replication, disk-to-disk backup, data archiving for future retrieval, and Information Lifecycle management (ILM). The idea is to leverage the parity computation that exists in RAID systems. By caching, transferring, and storing data parity or delta bytes of changes on a block as opposed to data block itself, substantial data reduction is possible without using sophisticated compression algorithms at the production side to minimize performance impacts upon production servers. Data can be computed using the parity/delta and previously existing data at mirror side, replication side, backup storage, or at retrieval time upon events such as failures or ILM operations.
    • 一种方法大大减少了要在网络存储系统中存储和传输的数据量。 优选地,网络存储系统通过镜像/复制,磁盘到磁盘备份,用于将来检索的数据归档和信息生命周期管理(ILM))提供持续的数据保护。 这个想法是利用RAID系统中存在的奇偶校验计算。 通过缓存,传输和存储块上的数据奇偶校验或增量字节更改与数据块本身相反,可以在生产端不使用复杂的压缩算法实现大量数据简化,从而最大限度地减少对生产服务器的性能影响。 数据可以使用奇偶校验/增量和以前存在的数据在镜像端,复制端,备份存储,或检索时间,例如故障或ILM操作。
    • 37. 发明授权
    • Storage array having multiple erasure correction and sub-stripe writing
    • 具有多个擦除校正和子条纹写入的存储阵列
    • US06748488B2
    • 2004-06-08
    • US09966842
    • 2001-09-28
    • James ByrdEbrahim HashemiManuel CisnerosAlex UminoJohn Schell
    • James ByrdEbrahim HashemiManuel CisnerosAlex UminoJohn Schell
    • G06F1200
    • G06F11/1076G06F2211/1057G06F2211/1066
    • A data storage subsystem including an array of storage devices and a storage controller is disclosed. In one embodiment, the array of storage devices stores information in multiple stripes. Each stripe may include a plurality of data blocks and redundancy information in the form of plurality of redundancy blocks. The redundancy information may be generated using an nth order generator polynomial such as a Reed Solomon code. The storage controller may be configured to perform modified read/write stripe updates by: (a) reading original data from a subset of data blocks in a target stripe; (b) reading the original redundancy information for that stripe; (c) comparing the original data with the new data to determine a data difference; (d) calculating a redundancy difference from the data difference; (e) applying the redundancy difference to the original redundancy information to obtain updated redundancy information, (f) writing the new data and updated redundancy information to the target stripe. Multiple erasure correction is also contemplated.
    • 公开了一种包括存储设备阵列和存储控制器的数据存储子系统。 在一个实施例中,存储设备阵列存储多条信息。 每个条带可以包括多个数据块和多个冗余块形式的冗余信息。 可以使用诸如里德所罗门码的第n阶生成多项式来生成冗余信息。 存储控制器可以被配置为通过以下操作来执行修改的读/写条带更新:(a)从目标条带中的数据块的子集读取原始数据; (b)读取该条纹的原始冗余信息; (c)将原始数据与新数据进行比较以确定数据差异; (d)从所述数据差计算冗余差; (e)将冗余差应用于原始冗余信息以获得更新的冗余信息,(f)将新数据和更新的冗余信息写入目标条带。 还设想了多次擦除校正。
    • 38. 发明申请
    • Storage array having multiple erasure correction and sub-stripe writing
    • 具有多个擦除校正和子条纹写入的存储阵列
    • US20030070042A1
    • 2003-04-10
    • US09966842
    • 2001-09-28
    • James ByrdEbrahim HashemiManuel CisnerosAlex UminoJohn Schell
    • G06F013/00
    • G06F11/1076G06F2211/1057G06F2211/1066
    • A data storage subsystem including an array of storage devices and a storage controller is disclosed. In one embodiment, the array of storage devices stores information in multiple stripes. Each stripe may include a plurality of data blocks and redundancy information in the form of plurality of redundancy blocks. The redundancy information may be generated using an nth order generator polynomial such as a Reed Solomon code. The storage controller may be configured to perform modified read/write stripe updates by: (a) reading original data from a subset of data blocks in a target stripe; (b) reading the original redundancy information for that stripe; (c) comparing the original data with the new data to determine a data difference; (d) calculating a redundancy difference from the data difference; (e) applying the redundancy difference to the original redundancy information to obtain updated redundancy information, (f) writing the new data and updated redundancy information to the target stripe. Multiple erasure correction is also contemplated.
    • 公开了一种包括存储设备阵列和存储控制器的数据存储子系统。 在一个实施例中,存储设备阵列存储多条信息。 每个条带可以包括多个数据块和多个冗余块形式的冗余信息。 可以使用诸如里德所罗门码的第n阶生成多项式来生成冗余信息。 存储控制器可以被配置为通过以下操作来执行修改的读/写条带更新:(a)从目标条带中的数据块的子集读取原始数据; (b)读取该条纹的原始冗余信息; (c)将原始数据与新数据进行比较以确定数据差异; (d)从所述数据差计算冗余差; (e)将冗余差应用于原始冗余信息以获得更新的冗余信息,(f)将新数据和更新的冗余信息写入目标条带。 还设想了多次擦除校正。
    • 39. 发明申请
    • Sparse byte enable indicator for high speed memory access arbitration method and apparatus
    • 稀疏字节使能指示灯用于高速存储器存取仲裁方法和装置
    • US20030002466A1
    • 2003-01-02
    • US09884270
    • 2001-06-19
    • Michael J. PetersJames R. Klobcar
    • H04Q007/24H04L012/66
    • G06F13/161G06F11/1076G06F2211/1066G06F2211/109
    • A sparse byte enable indicator for high speed memory access arbitration and a memory controller utilizing same is provided. According to the invention, a sparse byte enable indication is provided to the memory controller with or at about the same time that a request for a write to memory is received from a client. In response to receiving the sparse byte enable indication, the memory controller can begin to initiate a read-modify-write sequence. The present invention allows write operations involving less than complete data words in a first block of data to be completed in fewer clock cycles than in connection with conventional controllers that do not utilize a sparse byte enable indication. The present invention is applicable in connection with any device controlling access to memory in systems utilizing error correction code.
    • 提供用于高速存储器访问仲裁的稀疏字节使能指示符和使用它的存储器控​​制器。 根据本发明,在存储器控制器中提供稀疏字节使能指示,或者在从客户端接收对存储器的写入请求的同时提供。 响应于接收到稀疏字节使能指示,存储器控制器可以开始发起读 - 修改 - 写入序列。 本发明允许在与不与稀疏字节使能指示相关联的常规控制器的情况下以更少的时钟周期完成在第一数据块中涉及小于完整数据字的写入操作。 本发明可应用于利用纠错码的系统中控制对存储器的访问的设备。