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31. 发明专利

JP2012022767A Soft program of a non-volatile memory block 审中-公开
标题翻译：非易失性存储器块的软件程序
公开(公告)号：JP2012022767A
公开(公告)日：2012-02-02
申请号：JP2011153682
申请日：2011-07-12
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： JOHN S CHOI , HE ZHEN , MICHAEL A SADE
IPC分类号： G11C16/02
CPC分类号： G11C16/3468 , G11C16/0483 , G11C16/16
摘要： PROBLEM TO BE SOLVED: To provide a method of soft programming a non-volatile memory blocks.SOLUTION: The method of soft programming a non-volatile memory blocks includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage conditions is selected based on the results from soft programming the first subset of bits. The results of soft programming a second subset of bits is measured. The soft programming applies the initial voltage condition to the bits in the second subset of bits. The second subset comprises bits that are still over-erased when the step of selecting occurs. The result is that the soft programming for the second subset may begin at a more optimum point than the case of the soft program for the second subset for quickly achieving the needed soft programming to bring all of the bits within the desired erase condition.
摘要翻译：要解决的问题：提供一种对非易失性存储器块进行软编程的方法。解决方案：对非易失性存储器块进行软编程的方法包括擦除位并识别被擦除过度擦除的位。已经被擦除的位的第一个子集是软编程的。测量第一个子集的软编程的结果。基于来自软编程的第一比特的子集的结果，选择来自多个可能的电压条件的初始电压条件。测量第二个位子集的软编程结果。软编程将初始电压条件应用于位的第二子集中的位。第二子集包括当选择步骤发生时仍然被擦除的比特。结果是，第二子集的软编程可以比用于第二子集的软程序的情况更加优先的点开始，以便快速实现所需的软编程以使所有位都处于所需的擦除条件。版权所有（C）2012，JPO＆INPIT

32. 发明专利

JP2010279097A Battery charge circuit and battery charger 有权
标题翻译：电池充电电路和电池充电器
公开(公告)号：JP2010279097A
公开(公告)日：2010-12-09
申请号：JP2009126558
申请日：2009-05-26
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： AIURA MASAMI
IPC分类号： H02J7/10 , H01M10/44
CPC分类号： H02J7/0073
摘要： PROBLEM TO BE SOLVED: To provide a battery charge circuit having stable operation even in switching a charging mode, and to provide a battery charger.
SOLUTION: The battery charge circuit includes transistors 201, 202 for constituting a current mirror circuit for a transistor 200. A resistor R1 is connected to a source terminal of the transistor 201, and a resistor R2 is connected to a source terminal of the transistor 202. A switch circuit 14 is connected to each of the source terminals. The switch circuit 14 executes switching control in a small current mode and a fast mode. A current is supplied to the resistors R1, R2 from differently independent transistors to reduce a difference of phase delay due to CR time constant and thereby the operations of each charging mode, i.e., the small current mode or the fast mode can be stabilized.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：即使在切换充电模式时也提供具有稳定操作的电池充电电路，并且提供电池充电器。解决方案：电池充电电路包括用于构成晶体管200的电流镜电路的晶体管201,202。电阻器R1连接到晶体管201的源极端子，电阻器R2连接到晶体管201的源极端子晶体管202.开关电路14连接到每个源极端子。开关电路14以小电流模式和快速模式执行开关控制。电流由不同独立的晶体管提供给电阻器R1，R2，以减少由于CR时间常数导致的相位延迟差异，从而可以使每个充电模式，即小电流模式或快速模式的操作稳定。版权所有（C）2011，JPO＆INPIT

33. 发明专利

JP2010263375A Driver circuit 有权
标题翻译：驱动电路
公开(公告)号：JP2010263375A
公开(公告)日：2010-11-18
申请号：JP2009112158
申请日：2009-05-01
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： TAKI KONOSUKE
IPC分类号： H03K17/695
CPC分类号： H02P7/29
摘要： PROBLEM TO BE SOLVED: To provide a driver circuit for smoothly starting an output transistor and suppressing reduction in voltage. SOLUTION: A transistor 111 of a motor driver 11 is connected to a buffer 22 of a pre-driver 20. An external terminal TM1 of the motor driver 11 is connected to a regulator 26 to supply a voltage to transistors 231 and 232. Gate terminals of the transistors 231 and 232 are connected to drain terminals of the transistors 232 and 231, respectively. The transistor 231 is connected to a transistor 237 to which an input signal is supplied, and a transistor 233 is connected to a transistor 238 to which an inversion signal of the input signal is supplied. The external terminal TM1 is connected to the gate terminal of a transistor 21. The source terminal of the transistor 21 is connected to the buffer 22 through a transistor 234, and the drain terminal is connected to the regulator 26. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供用于平滑启动输出晶体管并抑制电压降低的驱动电路。解决方案：电动机驱动器11的晶体管111连接到预驱动器20的缓冲器22.电动机驱动器11的外部端子TM1连接到调节器26，以向晶体管231和232提供电压晶体管231和232的栅极端子分别连接到晶体管232和231的漏极端子。晶体管231连接到提供输入信号的晶体管237，并且晶体管233连接到晶体管238，晶体管238提供输入信号的反相信号。外部端子TM1连接到晶体管21的栅极端子。晶体管21的源极端子通过晶体管234连接到缓冲器22，漏极端子连接到调节器26。 C）2011，JPO＆INPIT

34. 发明专利

JP2008263627A Receiver and method therefor 有权
标题翻译：接收方及其方法
公开(公告)号：JP2008263627A
公开(公告)日：2008-10-30
申请号：JP2008133143
申请日：2008-05-21
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： LI JUNSONG , HENDRIX JON D , SEABERG CHARLES E , HO YUI-LUEN , INAYATULLAH AZFAR
IPC分类号： H04B7/005 , H04B7/08 , H04B1/10 , H04B1/28 , H04L1/06 , H04L27/38
CPC分类号： H04B7/0871 , H04B1/1081 , H04B1/28 , H04B7/084 , H04B7/0865 , H04B7/0891 , H04L1/0618 , H04L27/38
摘要： PROBLEM TO BE SOLVED: To prevent a receiving signal from being attenuated by a multi-path component. SOLUTION: One embodiment relates to a digital FM100 receiver having multiple sensors (for example, antennas) 102, 104. In one embodiment, the digital receiver includes a baseband unit 116 having a channel processing unit. In one embodiment, the channel processing unit is capable of calculating or estimating the phase difference between the incoming signals prior to combining them. One embodiment uses phase estimation method for diversity combining the signals, while another embodiment utilizes a hybrid phase lock loop method. Also, some embodiments provide for echo-canceling, after diversity combining. An alternate embodiment of the channel processing unit utilizes a space-time unit, to diversity combine and provide echo canceling for the incoming signals. Other embodiments of allow for the incoming signals from the multiple antennas, to pass through the baseband unit uncombined, as they are. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了防止接收信号被多径分量衰减。解决方案：一个实施例涉及具有多个传感器（例如，天线）102,104的数字FM100接收机。在一个实施例中，数字接收机包括具有信道处理单元的基带单元116。在一个实施例中，信道处理单元能够在组合它们之前计算或估计输入信号之间的相位差。一个实施例使用相位估计方法对信号进行分集，而另一个实施例利用混合锁相环方法。此外，一些实施例在分集组合之后提供回波消除。信道处理单元的另一实施例利用时空单元，对输入信号进行分集组合并提供回波消除。允许来自多个天线的输入信号的其他实施例原样通过基带单元未组合。版权所有（C）2009，JPO＆INPIT

35. 发明专利

JP2008258819A Pulse width modulated wave output circuit 有权
标题翻译：脉冲宽度调制波输出电路
公开(公告)号：JP2008258819A
公开(公告)日：2008-10-23
申请号：JP2007097406
申请日：2007-04-03
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： EGAWA KANJI , MURAKAMI SHINTARO
IPC分类号： H03K7/08 , H02M3/00
CPC分类号： H03K7/08
摘要： PROBLEM TO BE SOLVED: To provide a pulse width modulated wave output circuit capable of efficiently outputting accurate dual PWM waves. SOLUTION: In a dual PWM wave output circuit 20, two comparators (21, 22), a logical OR operation circuit 23 and a logical AND operation circuit 24 are provided. To the comparators (21, 22), a ramp voltage in which a phase is shifted at the same wave height is input from a voltage generator SG2. Further, the respective comparators compare a reference voltage Vc with the ramp voltage and supply a compared result to the logical OR operation circuit 23 and the logical AND operation circuit 24. Then, the logical OR operation circuit 23 outputs modulated waves PWM1 and the logical AND operation circuit 24 outputs modulated waves PWM2. As a result, the modulated waves (PWM1, PWM2) of different duties are output from the ramp voltage of different phases. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够有效地输出精确的双PWM波的脉宽调制波输出电路。
解决方案：在双PWM波形输出电路20中，提供两个比较器（21,22），逻辑或运算电路23和逻辑与运算电路24。对于比较器（21,22），从电压发生器SG2输入相位偏移相同波高的斜坡电压。此外，各比较器将参考电压Vc与斜坡电压进行比较，并将比较结果提供给逻辑或运算电路23和逻辑与运算电路24.然后，逻辑或运算电路23输出调制波PWM1和逻辑与运算电路24输出调制波PWM2。结果，不同占空比的调制波（PWM1，PWM2）从不同相位的斜坡电压输出。版权所有（C）2009，JPO＆INPIT

36. 发明专利

JP2008083831A Series regulator circuit 有权
标题翻译：系列调节器电路
公开(公告)号：JP2008083831A
公开(公告)日：2008-04-10
申请号：JP2006261121
申请日：2006-09-26
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： KIMURA HIROYUKI
IPC分类号： G05F1/56
CPC分类号： G05F1/56
摘要： PROBLEM TO BE SOLVED: To provide a series regulator circuit capable of being changed over to a mode of a different current consumption amount and being used as reducing current consumption, and allowing suppression of fluctuation in output voltage.
SOLUTION: In this series regulator circuit 10, a constant current source 20 connected to an input voltage VIN line is connected to a ground voltage GND line through a resistance element 21 and a transistor B1. Gate terminals of transistors M2, M4 are connected between the constant current source 20 and the transistor B1. The transistor M2 is connected to the input voltage VIN line through a transistor M1 becoming turned on to a high current mode. Source terminals of the transistors M2, M4 become an output terminal of the series regulator circuit 10. The output terminal is connected to the ground voltage GND line through a resistance element 23 and a transistor M3 becoming turned on to the high current mode, or through resistance elements 24, 25. A connection node of the resistance elements 24, 25 is connected to a base voltage of the transistor B1.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够转换为不同电流消耗量的模式的串联调节器电路，并且用作降低电流消耗，并且允许抑制输出电压的波动。
解决方案：在该串联调节器电路10中，连接到输入电压VIN线的恒流源20通过电阻元件21和晶体管B1连接到接地电压GND线。晶体管M2，M4的栅极端子连接在恒流源20和晶体管B1之间。晶体管M2通过导通到高电流模式的晶体管M1与输入电压VIN线相连。晶体管M2，M4的源极端子成为串联调节器电路10的输出端子。输出端子通过电阻元件23连接到接地电压GND线，并且晶体管M3变为导通到高电流模式，或者通过电阻元件24,25的电阻元件24,25的连接节点连接到晶体管B1的基极电压。版权所有（C）2008，JPO＆INPIT

37. 发明专利

JP2008021138A Series regulator circuit 有权
标题翻译：系列调节器电路
公开(公告)号：JP2008021138A
公开(公告)日：2008-01-31
申请号：JP2006192633
申请日：2006-07-13
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： KIMURA HIROYUKI
IPC分类号： G05F1/56
CPC分类号： G05F1/56
摘要： PROBLEM TO BE SOLVED: To provide a series regulator circuit which stably supplies voltage without depending on the capacity of a load by low current consumption.
SOLUTION: A constant current source IP connected to an input voltage VIN line is connected to a ground voltage GND line through a bipolar type transistor B1. To a connection node of the constant current source IP and the collector terminal of the transistor B1, the gate terminals of the transistors M1 and M2 of an n-channel MOS transistor are connected. The drain terminals of the transistors M1 and M2 are connected to the input voltage VIN line. The source terminal of the transistor M2 functions as an output terminal, and connected to the source terminal of the transistor M1 through a resistance element 14. The source terminal of the transistor M1 is connected to the ground voltage GND line through resistance elements 52 and 53. The connection node of the resistance elements 52 and 53 is connected to the base voltage of the transistor B1.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种串联调节器电路，其通过低电流消耗稳定地提供电压而不依赖于负载的容量。
解决方案：连接到输入电压VIN线的恒流源IP通过双极型晶体管B1连接到地电压GND线。连接到恒流源IP的连接节点和晶体管B1的集电极端子，连接n沟道MOS晶体管的晶体管M1和M2的栅极端子。晶体管M1和M2的漏极端子连接到输入电压VIN线。晶体管M2的源极端子用作输出端子，并且通过电阻元件14连接到晶体管M1的源极端子。晶体管M1的源极端子通过电阻元件52和53连接到地电压GND线电阻元件52和53的连接节点连接到晶体管B1的基极电压。版权所有（C）2008，JPO＆INPIT

38. 发明专利

JP2008020953A Semiconductor integrated circuit design method, and semiconductor integrated circuit design device 有权
标题翻译：半导体集成电路设计方法和半导体集成电路设计器件
公开(公告)号：JP2008020953A
公开(公告)日：2008-01-31
申请号：JP2006189730
申请日：2006-07-10
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： WATABE KENICHI
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5045 , G06F2217/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit design method and semiconductor integrated circuit design device capable of easily reducing off-leak current. SOLUTION: Wires connected to the input terminals of standard cells are exchanged mutually to change a gate net list 37 so as to reduce the off-leak current according to network probability 51 that is probability taken by the input of each standard cell and is generated by RTL function simulation or gate level function simulation, and a current consumption table 41 disposed in a technology library storage section 36. Based on the changed gate net list, a layout section 30 generates layout data where the wires connected to the input terminals of the standard cells are exchanged. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够容易地减少泄漏电流的半导体集成电路设计方法和半导体集成电路设计器件。解决方案：连接到标准单元的输入端的电线相互交换以改变栅极网列表37，以便根据网络概率51减少泄漏电流，这是由每个标准单元的输入的概率，通过RTL功能模拟或门级功能模拟产生，以及设置在技术库存储部分36中的电流消耗表41.根据改变的门网列表，布局部分30生成布局数据，其中连接到输入端的标准细胞被交换。版权所有（C）2008，JPO＆INPIT

39. 发明专利

JP2007335891A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007335891A
公开(公告)日：2007-12-27
申请号：JP2007209745
申请日：2007-08-10
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： BIKUUEN NGUYEN , J OLFEMI OROURAFUE , BAIKASU MAICHI , ORUBANMI ADCHUCHU , TOBIN PHILIP J
IPC分类号： H01L29/78 , H01L21/28 , H01L21/285 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L23/31 , H01L27/088 , H01L27/108 , H01L27/11 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L27/11 , H01L21/28044 , H01L21/28088 , H01L21/28568 , H01L21/76895 , H01L21/82345 , H01L23/3171 , H01L29/4925 , H01L29/4966 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To form a gate electrode that has a work function in the vicinity of an intermediate region in the band gap of a substrate material, eliminates the problem caused by fluorine, prevents the seeping of boron, eliminating complicated and excessive steps in manufacturing a metal-insulator-semiconductor field-effect transistor.
SOLUTION: Metallic semiconductor nitride gate electrodes 40, 70 are formed to be used in a semiconductor device 60. The electrodes 40, 70 can be formed by Sputter Deposition, Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD). The material etches silicon contained compounds and is etched by a conventional halogen-group etching chemical compound. The electrodes 40, 70 are relatively stable, can be formed relatively thinner than a conventional electrode and have a work function in the vicinity of the intermediate region in the band gap of a substance in the substrate 12.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了形成在基板材料的带隙中的中间区域附近具有功函数的栅电极，消除了由氟引起的问题，防止了硼的渗漏，消除了复杂的和制造金属 - 绝缘体 - 半导体场效应晶体管的过多步骤。解决方案：形成半导体器件60中使用的金属半导体氮化物栅电极40,70.电极40,70可以通过溅射沉积，低压化学气相沉积（LPCVD）或等离子体增强化学气相沉积（PECVD）。该材料蚀刻含硅化合物，并通过常规的卤素基蚀刻化合物进行蚀刻。电极40,70相对稳定，可以形成为比常规电极相对更薄，并且在基板12中的物质的带隙中的中间区域附近具有功函数。（C） 2008年，日本特许厅和INPIT

40. 发明专利

JP2007158331A Packaging method of semiconductor device 有权
标题翻译：半导体器件封装方法
公开(公告)号：JP2007158331A
公开(公告)日：2007-06-21
申请号：JP2006321047
申请日：2006-11-29
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： GAUTHAM VISWANADAM
IPC分类号： H01L23/12 , H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L21/486 , H01L21/561 , H01L23/49805 , H01L23/5389 , H01L24/97 , H01L25/105 , H01L2224/16245 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a manufacture method of a high-functionality laminated package with high reliability and at a low cost. SOLUTION: A packaging method of a semiconductor device includes a step for forming a through hole (12) in a base substrate (10) and a step for forming a conductive layer (18) by depositing a conductive material (14) on a first surface (16) of the base substrate (10) so that the through hole (12) is filled with the conductive material (14). A mutual connection trace and a pad (22) are formed by pattern-forming and etching the conductive layer (18). A conductive support body (24) is formed on the pad (22) so that the conductive support body (24) extends through each through hole (12). COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供高可靠性和低成本的高功能性层压包装的制造方法。解决方案：半导体器件的封装方法包括在基底衬底（10）中形成通孔（12）的步骤和通过将导电材料（14）沉积在其上形成导电层（18）的步骤基底基板（10）的第一表面（16），使得通孔（12）填充有导电材料（14）。通过图案形成和蚀刻导电层（18）形成相互连接迹线和焊盘（22）。导电支撑体（24）形成在垫（22）上，使得导电支撑体（24）延伸穿过每个通孔（12）。版权所有（C）2007，JPO＆INPIT

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