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31. 发明申请

US20120223331A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20120223331A1
公开(公告)日：2012-09-06
申请号：US13063745
申请日：2011-03-02
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/66803 , H01L29/7849
摘要： A semiconductor device comprises: a semiconductor substrate located on an insulating layer; and an insulator located on the insulating layer and embedded in the semiconductor substrate, wherein the insulator applies stress therein to the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a cavity within the semiconductor substrate so as to expose the insulating layer; forming an insulator in the cavity, wherein the insulator applies stress therein to the semiconductor substrate. It facilitates the reduction of the short channel effect, the resistance of source/drain regions and parasitic capacitance.
摘要翻译：半导体器件包括：位于绝缘层上的半导体衬底; 以及绝缘体，其位于所述绝缘层上并且嵌入所述半导体衬底中，其中所述绝缘体在其中向所述半导体衬底施加应力。一种形成半导体器件的方法包括：在绝缘层上形成半导体衬底; 在所述半导体衬底内形成空腔以暴露所述绝缘层; 在空腔中形成绝缘体，其中绝缘体在其中向半导体衬底施加应力。它有助于减少短沟道效应，源极/漏极区域的电阻和寄生电容。

32. 发明申请

US20120217553A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：US20120217553A1
公开(公告)日：2012-08-30
申请号：US13063737
申请日：2010-06-28
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7834 , H01L21/823443 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628
摘要： The present invention provides a semiconductor structure, comprising: a substrate; a gate formed on the substrate, and a source and drain formed in the substrate and disposed at two sides of the gate; raised portions formed on the source and the drain, respectively, a height of the raised portions being approximate to a height of the gate; and a metal silicide layer and contact holes formed on the raised portions and on the gate. By virtue of the raised portions added to the source/drain in an embodiment of the present invention, the height difference between the gate and the source/drain may be decreased, such that the formation of the contact holes becomes much easier.
摘要翻译：本发明提供一种半导体结构，包括：基板; 形成在基板上的栅极，以及形成在基板中并设置在栅极两侧的源极和漏极; 分别形成在源极和漏极上的凸起部分，凸起部分的高度接近门的高度; 以及形成在凸起部分和栅极上的金属硅化物层和接触孔。由于在本发明的一个实施例中，由于在源极/漏极上添加的凸起部分，栅极和源极/漏极之间的高度差可能会降低，使得接触孔的形成变得容易得多。

33. 发明申请

US20120181664A1 SUBSTRATE STRUCTURE FOR SEMICONDUCTOR DEVICE FABRICATION AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：用于半导体器件制造的衬底结构及其制造方法
公开(公告)号：US20120181664A1
公开(公告)日：2012-07-19
申请号：US13264063
申请日：2010-04-14
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/06 , H01L21/308 , H01L29/24 , H01L29/16
CPC分类号： H01L31/0392 , H01L31/035281 , Y02E10/50
摘要： The present invention proposes a strip plate structure and a method of manufacturing the same. In one embodiment, the strip plate structure comprises a strip plate array comprising a plurality of strip plates arranged in a predetermined direction with spacing, each of said strip plates including a first surface facing one side direction of the strip plate structure and a second surface facing an substantially opposite side direction of the strip plate structure; and a plurality of strip sheets, each strip sheet alternately abutting either the first surfaces or the second surfaces of two adjacent strip plates.
摘要翻译：本发明提出一种带状板结构及其制造方法。在一个实施例中，带状板结构包括带板阵列，其包括以预定方向排列的多个带状板，每个带状板包括面向带状板结构的一个侧面方向的第一表面和面向所述带状板结构的基本相反的侧面方向; 以及多个条状片，每个条带交替地邻接两个相邻带状板的第一表面或第二表面。

34. 发明申请

US20120168823A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120168823A1
公开(公告)日：2012-07-05
申请号：US13377766
申请日：2011-04-25
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/26 , H01L21/66
CPC分类号： H01L21/823807 , H01L21/02639 , H01L21/02647 , H01L21/76224 , H01L21/76229 , H01L21/823878 , H01L21/8258 , H01L29/66477
摘要： The present application discloses a semiconductor device and a method for forming the same. The method comprises: providing a first semiconductor layer and forming a first STI in the first semiconductor layer; determining a selected region in the first semiconductor layer, and making a portion of the first semiconductor layer in the selected region recessed; and in the selected region, epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the material of the second semiconductor layer is different from that of the first semiconductor layer. According to the present invention, a structure with a second semiconductor layer selectively epitaxially grown and embedded in the first semiconductor layer can be formed by a simple process, and defects generated during the epitaxial growth process can be further reduced.
摘要翻译：本申请公开了一种半导体器件及其形成方法。该方法包括：提供第一半导体层并在第一半导体层中形成第一STI; 确定所述第一半导体层中的选定区域，以及使所述选定区域中的所述第一半导体层的一部分凹陷; 并且在所选择的区域中，在第一半导体层上外延生长第二半导体层，其中第二半导体层的材料与第一半导体层的材料不同。根据本发明，可以通过简单的工艺形成具有选择性地外延生长并嵌入第一半导体层中的第二半导体层的结构，并且可以进一步减少在外延生长工艺期间产生的缺陷。

35. 发明申请

US20120104495A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120104495A1
公开(公告)日：2012-05-03
申请号：US13144182
申请日：2011-03-04
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/84 , H01L29/42384 , H01L29/4908 , H01L29/6675 , H01L29/78603 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention adjusts a threshold voltage with a common contact, which has a portion outside the source or drain region extending to the back-gate region and provides an electrical contact of the source or drain region and the back-gate region, which leads to a simple manufacturing process, an increased integration level and a lowered manufacture cost. Moreover, the asymmetric design of the back-gate structure further increases the threshold voltage and improves the performance of the device.
摘要翻译：本申请公开了一种半导体结构及其制造方法。根据本发明的半导体结构利用公共接触来调节阈值电压，该公共触点具有延伸到背栅极区域的源极或漏极区域之外的部分并且提供源极或漏极区域与背栅极的电接触区域，这导致简单的制造过程，增加的集成水平和降低的制造成本。此外，背栅结构的非对称设计进一步增加了阈值电压并提高了器件的性能。

36. 发明申请

US20120038006A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120038006A1
公开(公告)日：2012-02-16
申请号：US12937652
申请日：2010-07-25
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qiagqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qiagqing Liang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66636 , H01L29/66795 , H01L29/66803 , H01L29/7848 , H01L29/785
摘要： The present application discloses a semiconductor device comprising a fin of semiconductive material formed from a semiconductor layer over a semiconductor substrate and having two opposing sides perpendicular to the main surface of the semiconductor substrate; a source region and a drain region provided in the semiconductor substrate adjacent to two ends of the fin and being bridged by the fin; a channel region provided at the central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, and wherein the stack of gate dielectric and gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the semiconductor substrate, and insulated from the semiconductor substrate by an insulating layer. The semiconductor device has an improved short channel effect and a reduced parasitic capacitance and resistance, which contributes to an improved electrical property and facilitates scaling down of the transistor.
摘要翻译：本申请公开了一种半导体器件，其包括由半导体衬底上的半导体层形成并具有垂直于半导体衬底的主表面的两个相对侧的半导体材料的鳍; 源极区域和漏极区域，设置在所述半导体衬底中，邻近所述鳍片的两端并被所述鳍片桥接; 设置在所述翅片的中央部的通道区域; 以及设置在鳍的一侧的栅极电介质和栅极导体的堆叠，其中栅极导体通过栅极电介质与沟道区隔离，并且其中栅极电介质和栅极导体的堆叠远离翅片在平行于半导体衬底的主表面的方向上，并且通过绝缘层与半导体衬底绝缘。半导体器件具有改善的短沟道效应和减小的寄生电容和电阻，这有助于改善电性能并且有助于晶体管的缩小。

37. 发明申请

US20120013009A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120013009A1
公开(公告)日：2012-01-19
申请号：US12996721
申请日：2010-07-14
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76808 , H01L21/76831 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a local interconnect structure connected to the semiconductor substrate, and at least one via stack structure electrically connected to the local interconnect structure, wherein the at least one via stack structure comprises a via having an upper via and a lower via, the width of the upper via being greater than that of the lower via; a via spacer formed closely adjacent to the inner walls of the lower via; an insulation layer covering the surfaces of the via and the via spacer; a conductive plug formed within the space surrounded by the insulation layer, and electrically connected to the local interconnect structure. The present invention is applicable to manufacture of a via stack in the filed of manufacturing semiconductor.
摘要翻译：本发明公开了一种半导体结构及其制造方法。半导体结构包括半导体衬底，连接到半导体衬底的局部互连结构以及电连接到局部互连结构的至少一个通孔堆叠结构，其中至少一个通孔堆叠结构包括具有上通孔和下通孔，上通孔的宽度大于下通孔的宽度; 形成在靠近下通道的内壁的通孔间隔件; 覆盖通孔和通孔间隔物的表面的绝缘层; 形成在由所述绝缘层包围的空间内并且电连接到所述局部互连结构的导电插塞。本发明可应用于半导体制造领域中的通孔叠层的制造。

38. 发明申请

US20110316080A1 FIN TRANSISTOR STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译： FIN晶体管结构及其制造方法
公开(公告)号：US20110316080A1
公开(公告)日：2011-12-29
申请号：US12937486
申请日：2010-06-24
申请人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
发明人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/7851 , H01L29/66795
摘要： There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer.
摘要翻译：提供鳍式晶体管结构及其制造方法。翅片晶体管结构包括形成在半导体衬底上的鳍片，其中在用作晶体管结构的沟道区域的鳍片的一部分和衬底之间形成绝缘材料，并且在半导体衬底的剩余部分之间形成体半导体材料翅片和底物。由此，可以在保持低成本，高热传递等优点的同时，减小电流泄漏。

39. 发明申请

US20110298018A1 TRANSISTOR AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：晶体管及其制造方法
公开(公告)号：US20110298018A1
公开(公告)日：2011-12-08
申请号：US12937502
申请日：2010-06-28
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/28105 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： The invention provides a transistor, including: a substrate having a channel region; a source region and a drain region on two ends of the channel region of the substrate respectively; a gate high-K dielectric layer on a top surface of the substrate above the channel region between the source region and the drain region; an interfacial layer under the gate high-K dielectric layer, including a first portion near the source region and a second portion near the drain region, wherein an equivalent oxide thickness of the first portion is larger than that of the second portion. An asymmetric replacement metal gate forms an asymmetric interfacial layer, which is thin at the drain region side and thick at the source region side. At the thin drain region side, the short channel effect is significant and the asymmetric interfacial layer advantageously suppresses the short channel effect. At the thick source region side, the carrier mobility has a large influence on the device, and the asymmetric interfacial layer prevents the carrier mobility from decreasing. Further, the asymmetric replacement metal gate implements an asymmetric metal work function.
摘要翻译：本发明提供一种晶体管，包括：具有沟道区的衬底; 分别在所述衬底的沟道区域的两端上的源极区域和漏极区域; 位于源极区域和漏极区域之间的沟道区域上方的衬底顶表面上的栅极高K电介质层; 在栅极高K电介质层下面的界面层，包括靠近源区的第一部分和靠近漏极区的第二部分，其中第一部分的等效氧化物厚度大于第二部分的等效氧化物厚度。不对称替代金属栅极形成不对称界面层，其在漏极区侧较薄，在源极区侧较厚。在薄漏极侧，短沟道效应显着，不对称界面层有利地抑制了短沟道效应。在较厚的源极侧，载流子迁移率对器件的影响较大，不对称界面层阻止载流子迁移率降低。此外，不对称替代金属栅极实现了非对称金属功能。

40. 发明申请

US20110291184A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20110291184A1
公开(公告)日：2011-12-01
申请号：US13062911
申请日：2010-09-26
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/336 , B82Y99/00
CPC分类号： H01L29/78687 , H01L29/66545 , H01L29/66621 , H01L29/66772
摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate; an epitaxial semiconductor layer formed on two side portions of the semiconductor substrate; a gate stack formed at a central position on the semiconductor substrate and abutting the epitaxial semiconductor layer, the gate comprising a gate conductor layer and a gate dielectric layer which is sandwiched between the gate conductor layer and the semiconductor substrate and surrounding the lateral surfaces of the gate conductor layer; and a sidewall spacer formed on the epitaxial semiconductor layer and surrounding the gate. The method for manufacturing the above semiconductor structure comprises forming raised source/drain regions in the epitaxial semiconductor layer utilizing the sacrificial gate. The semiconductor structure and the method for manufacturing the same can simplify the fabrication process for an ultra-thin SOI transistor and reduce the ON-state resistance and power consumption of the transistor.
摘要翻译：本申请公开了一种半导体结构及其制造方法。半导体结构包括半导体衬底; 形成在所述半导体衬底的两个侧面上的外延半导体层; 形成在所述半导体衬底上的中心位置并与所述外延半导体层邻接的栅极叠层，所述栅极包括栅极导体层和栅极电介质层，所述栅极介电层夹在所述栅极导体层和所述半导体衬底之间，栅极导体层; 以及形成在外延半导体层上并围绕栅极的侧壁间隔物。制造上述半导体结构的方法包括利用牺牲栅极在外延半导体层中形成凸起的源/漏区。半导体结构及其制造方法可以简化超薄SOI晶体管的制造工艺，并降低晶体管的导通电阻和功耗。

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