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31. 发明授权

US08673704B2 FinFET and method for manufacturing the same 有权
标题翻译： FinFET及其制造方法
公开(公告)号：US08673704B2
公开(公告)日：2014-03-18
申请号：US13579192
申请日：2012-05-14
申请人： Huilong Zhu , Wei He , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Wei He , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/00
CPC分类号： H01L29/66795 , H01L29/785
摘要： A FinFET and a method for manufacturing the same are disclosed. The FinFET comprises an etching stop layer on a semiconductor substrate; a semiconductor fin on the etching stop layer; a gate conductor extending in a direction perpendicular to a length direction of the semiconductor fin and covering at least two side surfaces of the semiconductor fin; a gate dielectric layer between the gate conductor and the semiconductor fin; a source region and a drain region which are provided at two ends of the semiconductor fin respectively; and an interlayer insulating layer adjoining the etching stop layer below the gate dielectric layer, and separating the gate conductor from the etching stop layer and the semiconductor fin. A height of the fin of the FinFET is approximately equal to a thickness of a semiconductor layer for forming the semiconductor fin.
摘要翻译：公开了一种FinFET及其制造方法。 FinFET包括在半导体衬底上的蚀刻停止层; 在蚀刻停止层上的半导体鳍片; 栅极导体，其在与半导体鳍片的长度方向垂直的方向上延伸并覆盖半导体鳍片的至少两个侧面; 在栅极导体和半导体鳍片之间的栅介质层; 源极区和漏极区，分别设置在半导体鳍的两端; 以及与栅极电介质层下方的蚀刻停止层相邻的层间绝缘层，并且将栅极导体与蚀刻停止层和半导体鳍分离。 FinFET的鳍的高度近似等于用于形成半导体鳍的半导体层的厚度。

32. 发明授权

US08673701B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08673701B2
公开(公告)日：2014-03-18
申请号：US13376247
申请日：2011-08-02
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823828 , H01L21/823878 , H01L27/1203 , H01L29/4908 , H01L29/78603 , H01L29/78612
摘要： The present application discloses a semiconductor structure and method for manufacturing the same. The semiconductor structure comprises: an SOI substrate and a MOSFET formed on the SOI substrate, wherein the SOI substrate comprises, in a top-down fashion, an SOI layer, a first buried insulator layer, a buried semiconductor layer, a second buried insulator layer, and a semiconductor substrate, the buried semiconductor layer including a backgate region including a portion of the buried semiconductor layer doped with a dopant of a first polarity; the MOSFET comprises a gate stack and source/drain regions, the gate stack being formed on the SOI layer, and the source/drain regions being formed in the SOI layer at opposite sides of the gate stack; and the backgate region includes a counter-doped region, the counter-doped region is self-aligned with the gate stack and includes a dopant of a second polarity, and the second polarity is opposite to the first polarity. The embodiment of the present disclosure can be used for adjusting a threshold voltage of a MOSFET.
摘要翻译：本申请公开了一种半导体结构及其制造方法。半导体结构包括：SOI衬底和形成在SOI衬底上的MOSFET，其中SOI衬底以自顶向下的方式包括SOI层，第一掩埋绝缘体层，埋入半导体层，第二掩埋绝缘体层和半导体衬底，所述掩埋半导体层包括背栅区，所述背栅区包括掺杂有第一极性的掺杂剂的所述掩埋半导体层的一部分; MOSFET包括栅极堆叠和源极/漏极区，栅极堆叠形成在SOI层上，并且源极/漏极区域形成在栅极堆叠的相对侧的SOI层中; 并且所述背栅区域包括反掺杂区域，所述反掺杂区域与所述栅叠层自对准并且包括第二极性的掺杂剂，并且所述第二极性与所述第一极性相反。本公开的实施例可以用于调整MOSFET的阈值电压。

33. 发明授权

US08598662B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US08598662B2
公开(公告)日：2013-12-03
申请号：US13063745
申请日：2011-03-02
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/12 , H01L21/84 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/66803 , H01L29/7849
摘要： A semiconductor device comprises: a semiconductor substrate located on an insulating layer; and an insulator located on the insulating layer and embedded in the semiconductor substrate, wherein the insulator applies stress therein to the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a cavity within the semiconductor substrate so as to expose the insulating layer; forming an insulator in the cavity, wherein the insulator applies stress therein to the semiconductor substrate. It facilitates the reduction of the short channel effect, the resistance of source/drain regions and parasitic capacitance.
摘要翻译：半导体器件包括：位于绝缘层上的半导体衬底; 以及绝缘体，其位于所述绝缘层上并且嵌入所述半导体衬底中，其中所述绝缘体在其中向所述半导体衬底施加应力。一种形成半导体器件的方法包括：在绝缘层上形成半导体衬底; 在所述半导体衬底内形成空腔以暴露所述绝缘层; 在空腔中形成绝缘体，其中绝缘体在其中向半导体衬底施加应力。它有助于减少短沟道效应，源极/漏极区域的电阻和寄生电容。

34. 发明授权

US08587066B2 Structure and method having asymmetrical junction or reverse halo profile for semiconductor on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) 失效
标题翻译：具有半导体绝缘体（SOI）金属氧化物半导体场效应晶体管（MOSFET）的不对称结或反向晕轮廓的结构和方法
公开(公告)号：US08587066B2
公开(公告)日：2013-11-19
申请号：US13407264
申请日：2012-02-28
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L27/1207 , H01L21/76251 , H01L21/8221 , H01L27/0688 , H01L29/66545
摘要： A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided.
摘要翻译：提供了一种装置和方法，在一个实施例中提供了第一半导体器件，其包括在第一沟道区上的第一栅极结构，其中第一源区和第一漏区存在于第一沟道区的相对侧上，其中金属氮化物间隔物仅存在于第一沟道区的一侧。该器件还包括在第二沟道区上包括第二栅极结构的第二半导体器件，其中第二源区和第二漏区存在于第二沟道区的相对侧上。可以存在互连件，其提供第一半导体器件和第二半导体器件之间的电连通，其中第一半导体器件和第二半导体器件中的至少一个被反转。还提供了具有反向卤素掺杂剂分布的结构。

35. 发明申请

US20130299885A1 FINFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： FINFET及其制造方法
公开(公告)号：US20130299885A1
公开(公告)日：2013-11-14
申请号：US13579192
申请日：2012-05-14
申请人： Huilong Zhu , Wei He , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Wei He , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： A FinFET and a method for manufacturing the same are disclosed. The FinFET comprises an etching stop layer on a semiconductor substrate; a semiconductor fin on the etching stop layer; a gate conductor extending in a direction perpendicular to a length direction of the semiconductor fin and covering at least two side surfaces of the semiconductor fin; a gate dielectric layer between the gate conductor and the semiconductor fin; a source region and a drain region which are provided at two ends of the semiconductor fin respectively; and an interlayer insulating layer adjoining the etching stop layer below the gate dielectric layer, and separating the gate conductor from the etching stop layer and the semiconductor fin. A height of the fin of the FinFET is approximately equal to a thickness of a semiconductor layer for forming the semiconductor fin.
摘要翻译：公开了一种FinFET及其制造方法。 FinFET包括在半导体衬底上的蚀刻停止层; 在蚀刻停止层上的半导体鳍片; 栅极导体，其在与半导体鳍片的长度方向垂直的方向上延伸并覆盖半导体鳍片的至少两个侧面; 在栅极导体和半导体鳍片之间的栅介质层; 源极区和漏极区，分别设置在半导体鳍的两端; 以及与栅极电介质层下方的蚀刻停止层相邻的层间绝缘层，并且将栅极导体与蚀刻停止层和半导体鳍分离。 FinFET的鳍的高度近似等于用于形成半导体鳍的半导体层的厚度。

36. 发明授权

US08466500B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08466500B2
公开(公告)日：2013-06-18
申请号：US13063977
申请日：2011-02-24
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L33/12
CPC分类号： H01L29/7848 , H01L29/0653 , H01L29/1083 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7849
摘要： The present invention discloses a semiconductor device and a method for manufacturing the same, and relates to the field of semiconductor manufacturing. According to the present invention, the semiconductor device comprises: a semiconductor substrate; a gate region located above the semiconductor substrate; S/D regions located at both sides of the gate region and made of a stress material; wherein a concentrated stress region is formed between the gate region and the semiconductor substrate, and the concentrated stress region comprises an upper SOI layer adjacent to the gate region above, and a lower stress release layer adjacent to the semiconductor substrate below. The present invention applies to the manufacturing of a MOSFET.
摘要翻译：本发明公开了一种半导体器件及其制造方法，涉及半导体制造领域。根据本发明，半导体器件包括：半导体衬底; 位于半导体衬底上方的栅极区域; S / D区域位于栅极区域的两侧并由应力材料制成; 其中在所述栅极区域和所述半导体衬底之间形成集中应力区域，并且所述集中应力区域包括与所述栅极区域相邻的上部SOI层以及与所述半导体衬底相邻的较低应力释放层。本发明适用于MOSFET的制造。

37. 发明授权

US08440532B2 Structure and method for making metal semiconductor field effect transistor (MOSFET) with isolation last process 失效
标题翻译：制造具有隔离最后工艺的金属半导体场效应晶体管（MOSFET）的结构和方法
公开(公告)号：US08440532B2
公开(公告)日：2013-05-14
申请号：US12844478
申请日：2010-07-27
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/76224 , H01L21/76898 , H01L21/823481 , H01L27/1203
摘要： In one embodiment, a method of providing a semiconductor device is provided, in which instead of forming isolation regions before the formation of the semiconductor devices, the isolation regions are formed after the semiconductor devices. In one embodiment, the method includes forming a semiconductor device on a semiconductor substrate. A placeholder dielectric is formed on a portion of a first surface of the substrate adjacent to the semiconductor device. A trench is etched into the substrate from a second surface of the substrate that is opposite the first surface of the substrate, wherein the trench terminates on the placeholder dielectric. The trench is filled with a dielectric material.
摘要翻译：在一个实施例中，提供了提供半导体器件的方法，其中代替在形成半导体器件之前形成隔离区域，在半导体器件之后形成隔离区域。在一个实施例中，该方法包括在半导体衬底上形成半导体器件。在与半导体器件相邻的衬底的第一表面的一部分上形成占位电介质。沟槽从衬底的与衬底的第一表面相对的第二表面蚀刻到衬底中，其中沟槽终止在占位符电介质上。沟槽填充有电介质材料。

38. 发明申请

US20130049117A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130049117A1
公开(公告)日：2013-02-28
申请号：US13510807
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/84 , H01L27/1203
摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, a buried insulation layer, and a semiconductor layer, wherein the buried insulation layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the buried insulation layer; a plurality of MOSFETs being formed adjacently to each other in the SOI wafer, wherein each of the MOSFETs comprises a respective backgate being formed in the semiconductor substrate; and a plurality of shallow trench isolations, each of which being formed between respective adjacent MOSFETs to isolate the respective adjacent MOSFETs from each other, wherein the respective adjacent MOSFETs share a common backgate isolation region under the backgates in the semiconductor substrate, and a PNP junction or an NPN junction is formed by the common backgate isolation region and the backgates of the respective adjacent MOSFETs. According to the present disclosure, respective backgates of two adjacent MOSFETs are isolated from each other by the shallow trench isolation. Furthermore, the two adjacent MOSFETs are also isolated from each other by the PNP or NPN junction formed by the respective backgates of the two adjacent MOSFETs and the common backgate isolation. As a result, this device structure has a better insulation effect over the prior art MOSFET and it greatly reduces the possibility of breakthrough.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括：SOI晶片，其包括半导体衬底，掩埋绝缘层和半导体层，其中所述掩埋绝缘层设置在所述半导体衬底上，并且所述半导体层设置在所述掩埋绝缘层上; 在SOI晶片中彼此相邻形成的多个MOSFET，其中每个MOSFET包括形成在半导体衬底中的相应后栅; 以及多个浅沟槽隔离，其中每个分别形成在各个相邻的MOSFET之间，以将各个相邻的MOSFET彼此隔离，其中各个相邻的MOSFET共享在半导体衬底中的后栅上的公共后栅极隔离区，以及PNP结或NPN结由相应的相邻MOSFET的公共背栅隔离区和后沿形成。根据本公开，两个相邻MOSFET的相应背板通过浅沟槽隔离彼此隔离。此外，两个相邻的MOSFET也通过由两个相邻MOSFET的相应后沿和公共背栅隔离形成的PNP或NPN结彼此隔离。结果，该器件结构具有比现有技术的MOSFET更好的绝缘效果，并且大大降低了突破的可能性。

39. 发明申请

US20130001690A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US20130001690A1
公开(公告)日：2013-01-03
申请号：US13379111
申请日：2011-08-01
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78648
摘要： The present application provides a MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first buried insulating layer on the semiconductor substrate; a back gate formed in a first semiconductor layer which is on the first buried insulating layer; a second buried insulating layer on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is on the second buried insulating layer; a gate on the second semiconductor layer; and electrical contacts on the source/drain regions, the gate and the back gate, wherein the back gate is only under a channel region and one of the source/drain regions and not under the other of the source/drain regions, and a common electrical contact is formed between the back gate and the one of the source/drain regions. The MOSFET improves an effect of suppressing short channel effects by an asymmetric back gate, and reduces a footprint on a wafer by using the common conductive via.
摘要翻译：本申请提供了一种MOSFET及其制造方法。 MOSFET包括：半导体衬底; 半导体衬底上的第一掩埋绝缘层; 形成在第一掩埋绝缘层上的第一半导体层中的背栅; 在所述第一半导体层上的第二掩埋绝缘层; 源极/漏极区，形成在第二绝缘层上的第二半导体层中; 第二半导体层上的栅极; 以及源极/漏极区域，栅极和背栅极之间的电接触，其中后栅极仅在沟道区域和源极/漏极区域中的一个并且不在源极/漏极区域的另一个之下，并且具有公共在后栅极和源极/漏极区域之间形成电接触。 MOSFET改善了通过不对称背栅抑制短沟道效应的效果，并且通过使用公共导电通孔来减小晶片上的占位面积。

40. 发明申请

US20120153389A1 STRUCTURE AND METHOD HAVING ASYMMETRICAL JUNCTION OR REVERSE HALO PROFILE FOR SEMICONDUCTOR ON INSULATOR (SOI) METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) 失效
标题翻译：具有绝缘体（SOI）金属氧化物半导体场效应晶体管（MOSFET）的半导体的非对称结或反向HALO分布的结构和方法
公开(公告)号：US20120153389A1
公开(公告)日：2012-06-21
申请号：US13407264
申请日：2012-02-28
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
IPC分类号： H01L27/088
CPC分类号： H01L27/1207 , H01L21/76251 , H01L21/8221 , H01L27/0688 , H01L29/66545
摘要： A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided.
摘要翻译：提供了一种装置和方法，在一个实施例中提供了第一半导体器件，其包括在第一沟道区上的第一栅极结构，其中第一源区和第一漏区存在于第一沟道区的相对侧上，其中金属氮化物间隔物仅存在于第一沟道区的一侧。该器件还包括在第二沟道区上包括第二栅极结构的第二半导体器件，其中第二源区和第二漏区存在于第二沟道区的相对侧上。可以存在互连件，其提供第一半导体器件和第二半导体器件之间的电连通，其中第一半导体器件和第二半导体器件中的至少一个被反转。还提供了具有反向卤素掺杂剂分布的结构。

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