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31. 发明申请

US20100301449A1 METHODS AND APPARATUS FOR FORMING LINE AND PILLAR STRUCTURES FOR THREE DIMENSIONAL MEMORY ARRAYS USING A DOUBLE SUBTRACTIVE PROCESS AND IMPRINT LITHOGRAPHY 审中-公开
标题翻译：用三维存储器阵列形成直线和立柱结构的方法和装置，使用双重偏移过程和压印平版印刷
公开(公告)号：US20100301449A1
公开(公告)日：2010-12-02
申请号：US12856392
申请日：2010-08-13
申请人： Roy E. Scheuerlein , Yung-Tin Chen
发明人： Roy E. Scheuerlein , Yung-Tin Chen
IPC分类号： H01L27/02 , H01L21/02 , B29C59/02
CPC分类号： H01L27/1021 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/0337 , H01L21/3086 , H01L21/32139 , H01L21/76807 , H01L21/76817 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L29/8613 , H01L29/868 , H01L2221/1021
摘要： The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a double subtractive process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a double subtractive process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to rails for forming memory lines and at least one depth corresponds to pillars for forming memory cells. Numerous other aspects are disclosed.
摘要翻译：本发明提供使用多深度压印光刻掩模和双减法处理形成三维存储器阵列的系统，装置和方法。描述了用于制造三维存储器中的存储层的压印光刻掩模。掩模包括形成有用于在双减法中使用的转印材料中进行印记的特征的半透明材料，所述掩模具有多个印痕深度。至少一个压印深度对应于用于形成存储器线的轨道，并且至少一个深度对应于用于形成存储器单元的柱。公开了许多其他方面。

32. 发明授权

US07781269B2 Triangle two dimensional complementary patterning of pillars 有权
标题翻译：支柱三角形二维互补图案化
公开(公告)号：US07781269B2
公开(公告)日：2010-08-24
申请号：US12216109
申请日：2008-06-30
申请人： Chun-Ming Wang , Yung-Tin Chen , Roy E. Scheuerlein
发明人： Chun-Ming Wang , Yung-Tin Chen , Roy E. Scheuerlein
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/32139 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在器件层上形成多个间隔开的第一特征，其中每三个相邻的第一特征形成等边三角形，在第一特征上形成侧壁间隔物，用多个填料特征填充侧壁间隔件之间的空间，选择性地去除侧壁间隔物，以及使用至少多个填料特征作为掩模蚀刻至少一个器件层。一种器件包含位于衬底上方的多个底部电极，多个底部电极上的多个间隔开的支柱以及与多个支柱接触的多个上部电极。每三个相邻的柱形成等边三角形，每个柱包括半导体器件。多个支柱包括具有第一形状的多个第一支柱和具有不同于第一形状的第二形状的多个第二支柱。

33. 发明申请

US20090004879A1 TEST STRUCTURE FORMATION IN SEMICONDUCTOR PROCESSING 有权
标题翻译：半导体加工中的测试结构形成
公开(公告)号：US20090004879A1
公开(公告)日：2009-01-01
申请号：US11772128
申请日：2007-06-30
申请人： Calvin K. Li , Yung-Tin Chen , En-Hsing Chen , Paul Wai Kie Poon
发明人： Calvin K. Li , Yung-Tin Chen , En-Hsing Chen , Paul Wai Kie Poon
IPC分类号： H01L21/32
CPC分类号： H01L23/544 , G03F9/7046 , G03F9/7076 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent levels are patterned. The manner of using the mask also allows different types of test structures having different features to be formed. The different types of test structures can provide insight into performance characteristics of different types of devices.
摘要翻译：在半导体处理期间形成测试结构。测试结构允许在过程进行时监测性能特征。测试结构形成有一个单一的掩模，该掩模的使用方式也允许形成对准标记，这些对准标记在后续层次被图案化时不会相互干扰。使用掩模的方式也允许形成具有不同特征的不同类型的测试结构。不同类型的测试结构可以提供对不同类型设备的性能特征的洞察。

34. 发明申请

US20070184360A1 PHOTOMASK FEATURES WITH INTERIOR NONPRINTING WINDOW USING ALTERNATING PHASE SHIFTING 有权
标题翻译：带有内置非显示窗口的照片使用替代相位移
公开(公告)号：US20070184360A1
公开(公告)日：2007-08-09
申请号：US11615830
申请日：2006-12-22
申请人： Yung-Tin Chen
发明人： Yung-Tin Chen
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/30
摘要： Aspects of the present invention provide for a novel photomask for patterning features for an integrated circuit, the photomask including masked features having interior nonprinting windows. In some embodiments, the interior nonprinting window is an alternating phase shifter, while the area surrounding the masked features transmits light unshifted. In other embodiments, the interior nonprinting window transmits light unshifted, while the area surrounding the masked features is an alternating phase shifter. Thus any arrangement of features can be patterned with no phase conflict.
摘要翻译：本发明的方面提供了一种用于集成电路的图形化特征的新型光掩模，该光掩模包括具有内部非印刷窗口的掩蔽特征。在一些实施例中，内部非打印窗口是交替移相器，而围绕被掩蔽的特征的区域透射未被移动的光。在其他实施例中，内部非打印窗口透射未被移动的光，而围绕屏蔽特征的区域是交替移相器。因此，可以对任何特征的布置进行图案化而没有相位冲突。

35. 发明申请

US20230062718A1 THREE-DIMENSIONAL FERROELECTRIC RANDOM-ACCESS MEMORY (FERAM) 有权
公开(公告)号：US20230062718A1
公开(公告)日：2023-03-02
申请号：US17878686
申请日：2022-08-01
申请人： Yung-Tin Chen
发明人： Yung-Tin Chen
IPC分类号： H01L27/11597 , H01L27/11587 , G11C11/22
摘要： A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low- cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.

36. 发明授权

US11515330B2 Three-dimensional ferroelectric random-access memory (FeRAM) 有权
公开(公告)号：US11515330B2
公开(公告)日：2022-11-29
申请号：US16558072
申请日：2019-08-31
申请人： Yung-Tin Chen
发明人： Yung-Tin Chen
IPC分类号： H01L29/66 , H01L27/11597 , H01L29/78 , H01L27/1159
摘要： A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer, and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.

37. 发明授权

US10825834B1 Three-dimensional ferroelectric random-access memory (FeRAM) 有权
公开(公告)号：US10825834B1
公开(公告)日：2020-11-03
申请号：US16733102
申请日：2020-01-02
申请人： Yung-Tin Chen
发明人： Yung-Tin Chen
IPC分类号： H01L27/11 , H01L27/11597 , H01L27/11587 , G11C11/22
摘要： A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.

38. 发明授权

US08883589B2 Counter doping compensation methods to improve diode performance 有权
标题翻译：计数器掺杂补偿方法来提高二极管性能
公开(公告)号：US08883589B2
公开(公告)日：2014-11-11
申请号：US12892633
申请日：2010-09-28
申请人： Xiying Costa , Abhijit Bandyopadhyay , Kun Hou , Brian Le , Yung-Tin Chen
发明人： Xiying Costa , Abhijit Bandyopadhyay , Kun Hou , Brian Le , Yung-Tin Chen
IPC分类号： H01L21/8234 , H01L27/24 , H01L27/102 , H01L45/00
CPC分类号： H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1675
摘要： A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided.
摘要翻译：提供一种形成存储单元的方法，所述方法包括形成二极管，该二极管包括具有第一导电类型的第一区域，对二极管进行反掺杂以将第一区域改变为第二导电类型，以及形成串联耦合的存储元件与二极管。还提供其他方面。

39. 发明授权

US08879299B2 Non-volatile memory cell containing an in-cell resistor 有权
标题翻译：含有单元电阻的非易失性存储单元
公开(公告)号：US08879299B2
公开(公告)日：2014-11-04
申请号：US13552355
申请日：2012-07-18
申请人： Kun Hou , Yung-Tin Chen , Zhida Lan , Huiwen Xu
发明人： Kun Hou , Yung-Tin Chen , Zhida Lan , Huiwen Xu
IPC分类号： G11C11/36 , H01L27/24 , G11C17/16 , H01L45/00 , G11C13/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C17/16 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/51 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/146
摘要： A non-volatile memory cell includes a first electrode, a steering element, a metal oxide storage element located in series with the steering element, a dielectric resistor located in series with the steering element and the metal oxide storage element, and a second electrode.
摘要翻译：非易失性存储单元包括与转向元件串联设置的第一电极，操舵元件，金属氧化物存储元件，与转向元件和金属氧化物存储元件串联的介质电阻器和第二电极。

40. 发明授权

US08693233B2 Re-writable resistance-switching memory with balanced series stack 有权
标题翻译：具有平衡串联堆叠的可重写电阻切换存储器
公开(公告)号：US08693233B2
公开(公告)日：2014-04-08
申请号：US13363252
申请日：2012-01-31
申请人： Roy E Scheuerlein , Henry Chien , Zhida Lan , Yung-Tin Chen
发明人： Roy E Scheuerlein , Henry Chien , Zhida Lan , Yung-Tin Chen
IPC分类号： G11C11/00
CPC分类号： H01L45/146 , G11C5/02 , G11C8/08 , G11C8/12 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/33 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145
摘要： A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area.
摘要翻译：可重写电阻切换存储单元包括串联的第一和第二电容器。第一和第二电容器可以具有平衡的电气特性，以允许几乎同时进行相同方向的切换。第一电容器具有在第一和第二导电层之间的第一双极性电阻开关层，并且第二电容器在第三和第四导电层之间具有第二双极性电阻开关层。第一和第三导电层由普通材料制成，第二和第四导电层由普通材料制成。在一种方法中，第一和第二双极性电阻切换层由普通材料制成并且具有共同的厚度。在另一种方法中，第一和第二双极性电阻开关层由具有不同介电常数的材料制成，但它们的厚度与介电常数的差异成比例，以提供每单位面积的公共电容。

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