专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07424561B2 Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems 失效
标题翻译：使用分组，相干和非相干流量混合的系统来优化系统之间的传输
公开(公告)号：US07424561B2
公开(公告)日：2008-09-09
申请号：US11717511
申请日：2007-03-13
申请人： Barton J. Sano , Joseph B. Rowlands , Laurent R. Moll , Manu Gulati
发明人： Barton J. Sano , Joseph B. Rowlands , Laurent R. Moll , Manu Gulati
IPC分类号： G06F13/42 , G06F13/14 , G06F13/36 , G06F12/00
CPC分类号： G06F13/4022
摘要： An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.
摘要翻译：装置可以包括第一系统和第二系统。第一系统包括第一多个接口电路，并且第一多个接口电路中的每一个配置成耦合到单独的接口。第二系统包括第二多个接口电路，并且第二多个接口电路中的每一个被配置为耦合到单独的接口。第一多个接口电路的第一接口电路和第二多个接口电路的第二接口电路耦合到第一接口。第一接口电路和第二接口电路均被配置为在第一接口上传送分组，相关命令和非相干命令。

32. 发明授权

US07313146B2 Transparent data format within host device supporting differing transaction types 有权
标题翻译：支持不同事务类型的主机设备内的透明数据格式
公开(公告)号：US07313146B2
公开(公告)日：2007-12-25
申请号：US10684989
申请日：2003-10-14
申请人： Laurent R. Moll , Manu Gulati , Joseph B. Rowlands
发明人： Laurent R. Moll , Manu Gulati , Joseph B. Rowlands
IPC分类号： H04L12/56
CPC分类号： G06F3/00 , H04J3/16 , H04J3/22 , H04L12/50 , H04L12/56
摘要： A system for servicing packet data transactions and input/output transactions includes an input port, an output port, a node controller, a packet manager, and a switching module. The input port is receives communications from a communicatively coupled processing device that include packet data transactions and input/output transactions. The output port transmits communications to a communicatively coupled processing device that include packet data transactions and input/output transactions. The node controller communicatively couples to a system bus of the processing device and services input/output transactions. The packet manager communicatively couples to the system bus of the processing device and services packet data transactions. A switching module communicatively couples to the input port, the output port, the node controller, and the packet manager and services the exchange of transaction cells among the input port, the output port, the node controller, and the packet manager. Each transaction cell has a control tag and data and carrying all or a portion of a packet data transaction or an input/output transaction.
摘要翻译：用于对分组数据事务和输入/输出事务进行服务的系统包括输入端口，输出端口，节点控制器，分组管理器和交换模块。输入端口从包括分组数据事务和输入/输出事务的通信耦合的处理设备接收通信。输出端口将通信发送到包括分组数据事务和输入/输出事务的通信耦合处理设备。节点控制器通信地耦合到处理设备的系统总线并且服务输入/输出事务。分组管理器通信地耦合到处理设备的系统总线和服务分组数据事务。交换模块通信地耦合到输入端口，输出端口，节点控制器和分组管理器，并且为输入端口，输出端口，节点控制器和分组管理器之间的事务单元的交换提供服务。每个事务单元具有控制标签和数据，并且携带分组数据事务或输入/输出事务的全部或一部分。

33. 发明授权

US07227870B2 Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams 有权
标题翻译：包括用于分组和合并分组流的分组接口，交换机和分组DMA电路的系统
公开(公告)号：US07227870B2
公开(公告)日：2007-06-05
申请号：US10270016
申请日：2002-10-11
申请人： Barton J. Sano , Laurent R. Moll , Manu Gulati
发明人： Barton J. Sano , Laurent R. Moll , Manu Gulati
IPC分类号： H04L12/56
CPC分类号： H04L47/40
摘要： An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.
摘要翻译：集成电路包括用于接收分组的接收电路，用于发送分组的发送电路，用于向存储器控制器传送分组的分组DMA电路和用于选择性地将接收电路耦合到发送电路的开关。集成电路可以灵活地合并和拆分分组流，以提供要应用于分组流内的不同分组的各种分组处理/分组路由功能。装置可以包括两个或更多个集成电路，其可以在相应的接收和发送电路之间传送分组。

34. 发明授权

US07206879B2 Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems 有权
标题翻译：使用分组，相干和非相干流量混合的系统来优化系统之间的传输
公开(公告)号：US07206879B2
公开(公告)日：2007-04-17
申请号：US10269922
申请日：2002-10-11
申请人： Barton J. Sano , Joseph B. Rowlands , Laurent R. Moll , Manu Gulati
发明人： Barton J. Sano , Joseph B. Rowlands , Laurent R. Moll , Manu Gulati
IPC分类号： G06F13/42 , G06F13/14 , G06F13/36 , G06F12/00
CPC分类号： G06F13/4022
摘要： An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.
摘要翻译：装置可以包括第一系统和第二系统。第一系统包括第一多个接口电路，并且第一多个接口电路中的每一个被配置为耦合到单独的接口。第二系统包括第二多个接口电路，并且第二多个接口电路中的每一个被配置为耦合到单独的接口。第一多个接口电路的第一接口电路和第二多个接口电路的第二接口电路耦合到第一接口。第一接口电路和第二接口电路均被配置为在第一接口上传送分组，相关命令和非相干命令。

35. 发明授权

US06941440B2 Addressing scheme supporting variable local addressing and variable global addressing 有权
公开(公告)号：US06941440B2
公开(公告)日：2005-09-06
申请号：US10439297
申请日：2003-05-15
申请人： Laurent R. Moll , James D. Kelly , Manu Gulati , Koray Oner , Joseph B. Rowlands
发明人： Laurent R. Moll , James D. Kelly , Manu Gulati , Koray Oner , Joseph B. Rowlands
IPC分类号： G06F3/00 , G06F9/42 , G06F12/00 , G06F12/08
CPC分类号： G06F13/1684
摘要： A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式