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31. 发明授权

US08129285B2 Substrate processing system 失效
标题翻译：基板加工系统
公开(公告)号：US08129285B2
公开(公告)日：2012-03-06
申请号：US12501775
申请日：2009-07-13
申请人： Eiichi Nishimura
发明人： Eiichi Nishimura
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/6831 , H01J37/32743 , H01L21/67069 , H01L21/67207
摘要： A substrate processing method implemented in a substrate processing system that includes an etching apparatus that carries out plasma etching processing on a substrate and a vacuum-type substrate transferring apparatus to which the etching apparatus is connected is provided. A first step includes forming a protective film on a rear surface of the substrate before the plasma etching processing is carried out. The protective film prevents the rear surface of the substrate from being scratched by an electrostatic chuck that electrostatically attracts the substrate during the plasma etching processing. A second step includes electrostatically attracting the substrate to the electrostatic chuck such that the electrostatic chuck directly contacts the rear surface of the substrate and of carrying out the plasma etching processing on the substrate. A third step includes removing the protective film from the rear surface of the substrate after the plasma etching processing has been carried out.
摘要翻译：提供了一种在基板处理系统中实现的基板处理方法，该基板处理系统包括在基板上执行等离子体蚀刻处理的蚀刻装置和连接有蚀刻装置的真空型基板转印装置。第一步骤包括在进行等离子体蚀刻处理之前在基板的后表面上形成保护膜。保护膜防止在等离子体蚀刻处理期间静电吸引基板的静电卡盘刮擦基板的后表面。第二步骤包括静电吸引基板到静电卡盘，使得静电卡盘直接接触基板的后表面并对基板进行等离子体蚀刻处理。第三步骤包括在进行等离子体蚀刻处理之后从衬底的后表面去除保护膜。

32. 发明申请

US20110065049A1 PATTERN FORMING METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：图形形成方法和半导体器件的制造方法
公开(公告)号：US20110065049A1
公开(公告)日：2011-03-17
申请号：US12877218
申请日：2010-09-08
申请人： Masato KUSHIBIKI , Eiichi Nishimura
发明人： Masato KUSHIBIKI , Eiichi Nishimura
IPC分类号： G03F7/20
CPC分类号： G03F7/20 , G03F7/0045 , G03F7/0046 , G03F7/0397 , H01L21/02115 , H01L21/02164 , H01L21/02274 , H01L21/0228 , H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/3146 , H01L21/31608
摘要： A disclosed mask pattern forming method includes isotropically coating a surface of a resist pattern array having a predetermined line width with a silicon oxide film, embedding a gap in the resist pattern array coated by the silicon oxide film with a carbon film, removing the carbon film from the upper portion and etching back the carbon film while leaving the carbon film within the gap in any order, removing the remaining carbon film and etching back the upper portion of the resist pattern array to have a predetermined film thickness in any order, and forming a first mask pattern array which has a center portion having a predetermined width and film sidewall portions sandwiching the predetermined width, and arranged interposing a space width substantially the same as the predetermined line width with an asking process provided to the resist pattern array exposed from the removed silicon oxide film.
摘要翻译：所公开的掩模图案形成方法包括用氧化硅膜均匀地涂布具有预定线宽的抗蚀剂图案阵列的表面，在由氧化硅膜涂覆的抗蚀剂图案阵列中用碳膜包埋间隙，除去碳膜从上部开始蚀刻碳膜，同时以任何顺序将碳膜留在间隙内，除去剩余的碳膜并将抗蚀剂图案阵列的上部蚀刻回任何顺序具有预定的膜厚度，并且形成具有预定宽度的中心部分的第一掩模图案阵列和夹着预定宽度的膜侧壁部分，并且布置有与预定线宽基本相同的空间宽度，并提供给从去除氧化硅膜。

33. 发明授权

US07871908B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07871908B2
公开(公告)日：2011-01-18
申请号：US12407854
申请日：2009-03-20
申请人： Koichi Yatsuda , Eiichi Nishimura
发明人： Koichi Yatsuda , Eiichi Nishimura
IPC分类号： H01L21/425
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/31138 , H01L21/76811 , H01L21/76813 , H01L21/76816 , Y10S438/948 , Y10S438/975
摘要： The method of manufacturing a semiconductor device comprising: forming a first hard mask layer and a second hard mask layer on the layer to be etched (S11); a first groove-forming mask pattern forming process for forming a groove-forming mask pattern which has a first pitch, is formed of the second hard mask layer, and is used as an etching mask when forming groove patterns(S12-S14); and a first concave portion-forming mask pattern forming process for etching the first hard mask layer using the second resist pattern as an etching mask, wherein the second resist pattern is formed of the second resist layer having an opening portion that has a fourth pitch and the first organic layer having an opening portion that is connected to an opening portion of the second resist layer and has a smaller size than the opening portion of the second resist layer (S15-S18).
摘要翻译：制造半导体器件的方法包括：在被蚀刻层上形成第一硬掩模层和第二硬掩模层（S11）; 用于形成具有第一间距的沟槽形成掩模图案的第一凹槽形成掩模图案形成工艺由第二硬掩模层形成，并且在形成凹槽图案时用作蚀刻掩模（S12-S14）。以及使用第二抗蚀剂图案作为蚀刻掩模来蚀刻第一硬掩模层的第一凹部形成掩模图案形成工艺，其中第二抗蚀剂图案由具有第四间距的开口部分的第二抗蚀剂层形成，以及所述第一有机层具有与所述第二抗蚀剂层的开口部连接并且具有比所述第二抗蚀剂层的开口部小的尺寸的开口部（S15-S18）。

34. 发明申请

US20100173493A1 SUBSTRATE PROCESSING METHOD 有权
标题翻译：基板处理方法
公开(公告)号：US20100173493A1
公开(公告)日：2010-07-08
申请号：US12442075
申请日：2008-10-09
申请人： Masato Kushibiki , Eiichi Nishimura
发明人： Masato Kushibiki , Eiichi Nishimura
IPC分类号： H01L21/306
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31116 , H01L21/31122 , H01L21/31138 , H01L21/31144 , H01L21/32136
摘要： The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer which are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method includes a material deposition step of depositing a material on a side surface of the aperture and exposing a portion of the process layer by etching the exposed portion of the intermediate layer by plasma generated from a deposit gas, and an etching step of etching the exposed portion of the process layer.
摘要翻译：本发明提供一种基板处理方法，用于处理至少包括依次堆叠的处理层，中间层和掩模层的基板。掩模层包括被配置为暴露中间层的一部分的孔。基板处理方法包括：材料沉积步骤，其在所述孔的侧表面上沉积材料，并且通过用沉积气体产生的等离子体蚀刻所述中间层的暴露部分来暴露所述处理层的一部分;以及蚀刻步骤蚀刻处理层的暴露部分。

35. 发明申请

US20100068892A1 SUBSTRATE PROCESSING METHOD 有权
标题翻译：基板处理方法
公开(公告)号：US20100068892A1
公开(公告)日：2010-03-18
申请号：US12558047
申请日：2009-09-11
申请人： Masato KUSHIBIKI , Eiichi Nishimura
发明人： Masato KUSHIBIKI , Eiichi Nishimura
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31138 , H01L21/31144
摘要： In a substrate processing method of processing a substrate in which a processing target layer, an intermediate layer, and a mask layer are stacked one on top of another, the mask layer having an opening that partially exposes the intermediate layer, a thickness of the mask layer is increased by depositing deposits on an upper surface of the mask layer with plasma generated from a mixed gas of SF6 gas and a depositive gas represented in a general equation, CxHyFz (where, x, y, and z are positive integers).
摘要翻译：在其中处理目标层，中间层和掩模层层叠在一起的衬底的衬底处理方法中，具有部分地暴露中间层的开口的掩模层，掩模的厚度通过在SF6气体和通式（C x H y F z（其中x，y和z是正整数）表示的沉积气体的混合气体产生的等离子体中，在掩模层的上表面上沉积沉积物来增加层。

36. 发明申请

US20100040980A1 METHOD AND APPARATUS FOR REFORMING FILM AND CONTROLLING SLIMMING AMOUNT THEREOF 审中-公开
标题翻译：用于改造薄膜和控制薄膜的方法和装置
公开(公告)号：US20100040980A1
公开(公告)日：2010-02-18
申请号：US12581963
申请日：2009-10-20
申请人： Eiichi Nishimura , Takashi Tanaka , Gen You , Minoru Honda , Mitsuaki Iwashita
发明人： Eiichi Nishimura , Takashi Tanaka , Gen You , Minoru Honda , Mitsuaki Iwashita
IPC分类号： G03F7/20
CPC分类号： G03F7/40
摘要： In a film reforming method for reforming a film layer to be reformed by irradiating electron beams thereon, the electron beams are irradiated in a state where the film layer is cooled. Further, in a slimming amount controlling method for controlling a slimming amount of a resist film layer, the slimming amount thereof is controlled by the irradiation amount of electron beams irradiated thereon in a state where the resist film layer having a specified opening dimension is cooled. Furthermore, in a film reforming apparatus including a mounting unit for mounting thereon an object to be processed and an electron beam irradiating unit for irradiating electron beams on the object disposed on the mounting unit to thereby reform a film layer to be reformed, formed on an object, the electron beams are irradiated from the electron beam irradiating unit in a state where the film layer is cooled by a cooling unit provided in the mounting unit.
摘要翻译：在通过在其上照射电子束来重整薄膜层的薄膜重整方法中，在薄膜层被冷却的状态下照射电子束。此外，在用于控制抗蚀剂膜层的减肥量的减肥量控制方法中，在具有指定的开口尺寸的抗蚀剂膜层被冷却的状态下，通过照射在其上的电子束的照射量来控制其减肥量。此外，在包括用于在其上安装待处理物体的安装单元和用于在设置在安装单元上的物体上照射电子束的电子束照射单元的薄膜重整设备中，从而将形成在其上的膜层重新形成在由设置在安装单元中的冷却单元冷却膜层的状态下，从电子束照射单元照射电子束。

37. 发明申请

US20100029086A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND STORAGE MEDIUM 审中-公开
标题翻译：制造半导体器件和存储介质的方法
公开(公告)号：US20100029086A1
公开(公告)日：2010-02-04
申请号：US12555283
申请日：2009-09-08
申请人： Hidenori Miyoshi , Eiichi Nishimura , Kazuhiro Kubota
发明人： Hidenori Miyoshi , Eiichi Nishimura , Kazuhiro Kubota
IPC分类号： H01L21/306
CPC分类号： H01L21/02063 , H01L21/02068 , H01L21/32136 , H01L21/76814
摘要： A semiconductor device having high reliability is provided by reducing fluorine remaining in a metal forming the semiconductor device. Specifically disclosed is a method for manufacturing a semiconductor device including a fluoride removal step for removing a metal fluoride produced on a metal forming an electrode or wiring of a semiconductor device which is formed on a substrate to be processed. This method for manufacturing a semiconductor device is characterized in that the metal fluoride is removed by supplying formic acid in a gaseous state to the substrate to be processed in the fluoride removal step.
摘要翻译：通过减少形成半导体器件的金属中残留的氟来提供具有高可靠性的半导体器件。具体公开了一种半导体装置的制造方法，该半导体装置具有除去形成在被处理基板上的半导体装置的电极或配线的金属上产生的金属氟化物的氟化物除去工序。这种半导体装置的制造方法的特征在于，通过在氟化物除去工序中向被处理基板供给气态的甲酸，除去金属氟化物。

38. 发明申请

US20090209108A1 SUBSTRATE PROCESSING METHOD 审中-公开
标题翻译：基板处理方法
公开(公告)号：US20090209108A1
公开(公告)日：2009-08-20
申请号：US12388858
申请日：2009-02-19
申请人： Tsuyoshi MORIYA , Eiichi Nishimura
发明人： Tsuyoshi MORIYA , Eiichi Nishimura
IPC分类号： H01L21/3065 , H01L21/306
CPC分类号： H01L21/02068
摘要： A substrate processing method that can prevent a decrease in the yield of semiconductor devices manufactured from substrates. A gas containing fluorine atoms is supplied into a chamber, and then chlorine gas is supplied into the chamber. Further, a gas containing nitrogen atoms is supplied into the chamber.
摘要翻译：可以防止由基板制造的半导体器件的产量降低的基板处理方法。将含有氟原子的气体供给到室内，然后向室内供给氯气。此外，将含有氮原子的气体供给到室中。

39. 发明申请

US20090011605A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090011605A1
公开(公告)日：2009-01-08
申请号：US12216154
申请日：2008-06-30
申请人： Yuki Chiba , Eiichi Nishimura , Ryuichi Asako
发明人： Yuki Chiba , Eiichi Nishimura , Ryuichi Asako
IPC分类号： H01L21/3065
CPC分类号： H01L21/02063 , H01J37/32522 , H01J2237/2001 , H01L21/3105 , H01L21/31116 , H01L21/31138 , H01L21/76807 , H01L21/76814 , H01L21/76826
摘要： The present invention is an apparatus for manufacturing a semiconductor device comprising: a process vessel including a stage on which a substrate is placed, the substrate having a low dielectric constant film with a resist pattern being formed in an upper layer of the low dielectric constant film; an etching-gas supply unit that supplies an etching gas into the process vessel so as to etch the low dielectric constant film; an ashing-gas unit means that supplies an ashing gas into the process vessel so as to ash the resist pattern formed in the upper layer of the low dielectric constant film after the low dielectric constant film has been subjected to an etching process; a plasma generating means that generates a plasma by supplying an energy to the etching gas and the ashing gas in the process vessel; a unit that supplies a dipivaloylmethane gas into the process vessel, after the low dielectric constant film has been subjected to an ashing process, in order to recover a damage layer of the low dielectric constant film which has been damaged by the plasma; and a heating unit that enables the dipivaloylmethane gas to come into contact with a surface of the substrate under a heated condition.
摘要翻译：本发明是一种半导体器件的制造装置，其特征在于，包括：处理容器，其具有载置基板的载物台，所述基板具有低介电常数膜，所述低介电常数膜形成在所述低介电常数膜的上层中 ; 蚀刻气体供给单元，其将蚀刻气体供给到所述处理容器中，以蚀刻所述低介电常数膜; 灰化单元意味着在低介电常数薄膜进行了蚀刻处理之后，将灰化气体供给到处理容器中，以使在低介电常数膜的上层形成的抗蚀剂图案灰化; 等离子体产生装置，其通过向处理容器中的蚀刻气体和灰化气体供应能量来产生等离子体; 在低介电常数薄膜已进行灰化处理之后，向该处理容器中供给二过代甲烷气体的单元，以回收已被等离子体损坏的低介电常数膜的损伤层; 以及加热单元，其使得二辛酰甲烷气体在加热条件下与基材的表面接触。

40. 发明申请

US20080124936A1 MANUFACTURING METHOD OF CAPACITOR ELECTRODE, MANUFACTURING SYSTEM OF CAPACITOR ELECTRODE, AND STORAGE MEDIUM 有权
标题翻译：电容器电极的制造方法，电容器电极的制造系统和存储介质
公开(公告)号：US20080124936A1
公开(公告)日：2008-05-29
申请号：US11946289
申请日：2007-11-28
申请人： Eiichi Nishimura
发明人： Eiichi Nishimura
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/67069 , H01L28/91
摘要： A method for manufacturing a capacitor electrode by removing a silicon oxide film on a surface of a substrate, including: transforming the silicon oxide film into a reaction product by supplying a gas containing a halogen element to chemically react with the silicon oxide film while controlling temperature of the substrate to a first process temperature; and removing the silicon oxide film transformed to the reaction product while controlling the temperature of the substrate to a second process temperature higher than the first process temperature. The silicon oxide film is a BPSG film.
摘要翻译：一种通过去除衬底表面上的氧化硅膜来制造电容器电极的方法，包括：通过提供含有卤素元素的气体将氧化硅膜转化为反应产物，以与氧化硅膜发生化学反应同时控制温度的基底到第一工艺温度; 以及在将基板的温度控制到高于第一处理温度的第二处理温度的同时除去转化为反应产物的氧化硅膜。氧化硅膜是BPSG膜。

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