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31. 发明授权

US07521750B2 Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same 有权
标题翻译：具有多位非易失性存储单元的半导体器件及其制造方法
公开(公告)号：US07521750B2
公开(公告)日：2009-04-21
申请号：US12017239
申请日：2008-01-21
申请人： Bo-Young Seo , Hee-Seog Jeon , Sung-Taeg Kang
发明人： Bo-Young Seo , Hee-Seog Jeon , Sung-Taeg Kang
IPC分类号： H01L29/76
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5692 , G11C16/0458 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A nonvolatile semiconductor device includes a pair of multi-bit nonvolatile memory unit cells. Each unit cell includes a grid type semiconductor body in which a plurality of parallel semiconductor bodies extend in a first direction and a plurality of parallel semiconductor bodies extend in a second direction perpendicular to the first direction, a channel region formed in a partial region of the semiconductor body along circumferences of the semiconductor bodies that extend in the first direction, a charge storage region formed on the channel region, a plurality of control gates, which are formed on the charge storage region and wherein each of the plurality of control gates is adapted to receive separate control voltages. Each unit cell further includes source and drain regions aligned on both sides of the plurality of control gates and formed in the semiconductor bodies, wherein the pair of unit cells share the source region, and the source region is formed at a cross point of the grid.
摘要翻译：非易失性半导体器件包括一对多位非易失性存储单元。每个单电池包括栅格型半导体本体，其中多个平行的半导体本体在第一方向上延伸，并且多个平行的半导体本体在垂直于第一方向的第二方向上延伸，沟道区形成在半导体本体沿着在第一方向上延伸的半导体本体的周边，形成在沟道区上的电荷存储区域，形成在电荷存储区域上的多个控制栅极，并且其中多个控制栅极中的每一个被适配以接收单独的控制电压。每个单元还包括在多个控制栅极的两侧对准并形成在半导体主体中的源极和漏极区域，其中该对单元电池共享源极区域，并且源极区域形成在栅极的交叉点处。

32. 发明授权

US07512003B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07512003B2
公开(公告)日：2009-03-31
申请号：US11789003
申请日：2007-04-23
申请人： Hyun-Khe Yoo , Ji-Do Ryu , Bo-Young Seo , Chang-Min Jeon , Hee-Seog Jeon , Sung-Gon Choi , Jeong-Uk Han
发明人： Hyun-Khe Yoo , Ji-Do Ryu , Bo-Young Seo , Chang-Min Jeon , Hee-Seog Jeon , Sung-Gon Choi , Jeong-Uk Han
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C7/18 , G11C16/24 , G11C2207/002
摘要： A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.
摘要翻译：非易失性存储器件包括存储器单元块，第一切换块和第二切换块。多个存储单元布置在存储单元块中，并且每个存储单元包括具有浮置栅极和控制栅极的存储晶体管，并连接到局部位线，并且包括串联连接到存储晶体管的选择晶体管它连接到源线。第一切换块选择性地将全局位线连接到本地位线，而第二切换块以预定位数为单位来控制存储单元块中的存储单元。第一切换块包括在全局位线和局部位线之间并联连接的至少两个开关器件。

33. 发明申请

US20080253190A1 Non-volatile memory device and method of operating the same 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20080253190A1
公开(公告)日：2008-10-16
申请号：US11903482
申请日：2007-09-21
申请人： Chang-Min Jeon , Hee-Seog Jeon , Hyun-Khe Yoo , Sung-Gon Choi , Bo-Young Seo , Ji-Do Ryu
发明人： Chang-Min Jeon , Hee-Seog Jeon , Hyun-Khe Yoo , Sung-Gon Choi , Bo-Young Seo , Ji-Do Ryu
IPC分类号： G11C16/06 , H01L29/788
CPC分类号： G11C16/0433 , H01L27/115 , H01L27/11524
摘要： The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled.
摘要翻译：本发明涉及一种非易失性存储器件及其操作方法。非易失性存储器件包括连接到第n位线的第一晶体管和连接到第（n + 1）位线的第二晶体管。第一晶体管和第二晶体管串联耦合在第n位线和第（n + 1）位线之间。非易失性存储器件可以包括2晶体管1位单元，其中存储单元的漏极区域和源极区域具有相同或相似的结构。由于根据本发明的非易失性存储器件的单元阵列可以包括2-晶体管2位单位单元，所以非易失性存储器件的存储容量可以加倍。

34. 发明授权

US07339232B2 Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same 有权
标题翻译：具有多位非易失性存储单元的半导体器件及其制造方法
公开(公告)号：US07339232B2
公开(公告)日：2008-03-04
申请号：US11256554
申请日：2005-10-21
申请人： Bo-Young Seo , Hee-Seog Jeon , Sung-Taeg Kang
发明人： Bo-Young Seo , Hee-Seog Jeon , Sung-Taeg Kang
IPC分类号： H01L29/76
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5692 , G11C16/0458 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge storage region. The charge storage regions are for accumulating charges within each of the plurality of transistors of the memory unit cell. Each of the control gates are connected to at least one control voltage to shift a threshold voltage in each of the plurality of transistors for storing multi-bit per unit cell.
摘要翻译：提供具有多位非易失性存储单元的半导体器件。半导体器件包括共享源极和漏极区域并具有多个晶体管的多位非易失性存储单元单元。多个晶体管各自包括至少一个控制栅极和至少一个电荷存储区域。电荷存储区域用于在存储单元的多个晶体管的每一个内累积电荷。每个控制栅极被连接到至少一个控制电压以移位多个晶体管中的每个晶体管中的阈值电压以存储每位单元的多位。

35. 发明申请

US20060108610A1 Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method 有权
公开(公告)号：US20060108610A1
公开(公告)日：2006-05-25
申请号：US11329217
申请日：2006-01-10
申请人： Sung-Taeg Kang , Jeong-Uk Han , Sung-Woo Park , Seung-Beom Yoon , Ji-Hoon Park , Bo-Young Seo
发明人： Sung-Taeg Kang , Jeong-Uk Han , Sung-Woo Park , Seung-Beom Yoon , Ji-Hoon Park , Bo-Young Seo
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L21/28273 , H01L21/0214 , H01L21/3144 , H01L29/513 , H01L29/7881
摘要： In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.

36. 发明授权

US07041557B2 Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method 有权
标题翻译：使用热处理制造薄介电层的方法和使用该方法形成的半导体器件
公开(公告)号：US07041557B2
公开(公告)日：2006-05-09
申请号：US10832952
申请日：2004-04-27
申请人： Sung-Taeg Kang , Jeong-Uk Han , Sung-Woo Park , Seung-Beom Yoon , Ji-Hoon Park , Bo-Young Seo
发明人： Sung-Taeg Kang , Jeong-Uk Han , Sung-Woo Park , Seung-Beom Yoon , Ji-Hoon Park , Bo-Young Seo
IPC分类号： H01L21/366
CPC分类号： H01L21/0214 , H01L21/02249 , H01L21/02252 , H01L21/28273 , H01L21/3144
摘要： In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.
摘要翻译：在根据该方法形成的半导体器件和半导体器件的形成方法中，在下导电层和上导电层之间设置有薄的电介质层。在一个实施例中，薄介电层包括栅极间电介质层，下导电层包括浮动栅极，上介电层包括晶体管的控制栅极，例如非易失性存储单元晶体管。使用导致下面的浮置栅极的表面粗糙度降低的热处理工艺形成薄介电层，并且导致在浮动栅极上形成薄的氧氮化硅层。以这种方式，薄介电层提供在下浮动栅极和上控制栅极之间增加的电容耦合。这也导致降低的编程电压，擦除晶体管的电压和读取电压，同时将阈值电压保持在期望的范围内。此外，晶体管和所得到的存储单元的尺寸可以被最小化，并且减轻了对电路中的高电压区域的需要，因为假设降低的编程电压，不需要泵浦电路。

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