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31. 发明授权

US6096648A Copper/low dielectric interconnect formation with reduced electromigration 有权
标题翻译：具有减少电迁移的铜/低介电互连形成
公开(公告)号：US6096648A
公开(公告)日：2000-08-01
申请号：US237584
申请日：1999-01-26
申请人： Sergey Lopatin , Takeshi Nogami , Robin W. Cheung , Christy Mei-Chu Woo , Guarionex Morales
发明人： Sergey Lopatin , Takeshi Nogami , Robin W. Cheung , Christy Mei-Chu Woo , Guarionex Morales
IPC分类号： H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76886 , H01L21/76819 , H01L21/76835 , H01L21/76837 , H01L21/76885
摘要： A method of metallizing a semiconductor chip with copper including an inlaid low dielectric constant layer. The method includes the step of depositing a barrier layer on the surface of the semiconductor chip. Next, a copper seed layer is deposited on the barrier layer, and then the copper seed layer is annealed. Microlithography is then performed on the semiconductor chip to form a plurality of wiring line paths with a patterned photoresist layer. After the wiring line paths are formed a copper conductive layer is electroplated to the surface of the semiconductor chip. Next, the patterned photoresist layer is stripped off of the surface of the semiconductor chip. In addition, portions of the barrier layer and the copper seed layer that were covered by the patterned photoresist layer are also removed. A low dielectric constant layer is then deposited on the semiconductor chip to fill the gaps between the newly created copper conductive lines.
摘要翻译：一种用包括嵌入的低介电常数层的铜对半导体芯片进行金属化的方法。该方法包括在半导体芯片的表面上沉积阻挡层的步骤。接下来，在阻挡层上沉积铜籽晶层，然后对铜籽晶层进行退火。然后在半导体芯片上进行微光刻，以形成具有图案化光致抗蚀剂层的多条布线路径。在形成布线路径之后，将铜导电层电镀到半导体芯片的表面。接下来，将图案化的光致抗蚀剂层剥离出半导体芯片的表面。此外，也去除了被图案化光致抗蚀剂层覆盖的阻挡层和铜籽晶层的部分。然后在半导体芯片上沉积低介电常数层以填充新生成的铜导线之间的间隙。

32. 发明授权

US6083842A Fabrication of a via plug having high aspect ratio with a diffusion barrier layer effectively surrounding the via plug 有权
标题翻译：与扩散阻挡层具有高纵横比的通孔塞有效地围绕通孔塞
公开(公告)号：US6083842A
公开(公告)日：2000-07-04
申请号：US253479
申请日：1999-02-19
申请人： Robin Cheung , Sergey Lopatin
发明人： Robin Cheung , Sergey Lopatin
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/76852 , H01L21/76843 , H01L21/76885
摘要： A method for efficiently fabricating a via plug having high aspect ratio within an insulating layer with a diffusion barrier layer effectively surrounding the via plug. The method includes the steps of depositing a via photoresist layer over a first metal line of a first conductive material and etching a via hole in the via photoresist layer. The first conductive material of the first metal line is exposed at a bottom wall of the via hole. A via plug of a second conductive material is deposited into the via hole, and the via plug makes a conductive path with the first metal line. The via photoresist layer is then removed such that any side wall of the via plug is exposed. A first diffusion barrier layer is then deposited onto any exposed surface of the second conductive material of the via plug. A via insulating layer is then spin-coated to surround the via plug and a trench insulating layer is also deposited over the via insulating layer. A trench is then etched over the via plug having the first diffusion barrier layer, and the via plug with the first diffusion barrier layer is exposed as part of a bottom wall of the trench. A second diffusion barrier layer is then deposited onto the walls of the trench, and a third conductive material is deposited into the trench to form a second metal line. The second metal line makes a conductive path with the second conductive material of the via plug. Thus, the present invention avoids the prior art method of depositing a diffusion barrier layer into the via hole within a via insulating layer before filling the via hole with the via plug. With the present invention, a via plug with high aspect ratio may be efficiently formed with the diffusion barrier layer effectively surrounding the via plug.
摘要翻译：一种用于在绝缘层内有效地制造具有高纵横比的通孔的方法，其中扩散阻挡层有效围绕通孔塞。该方法包括以下步骤：在第一导电材料的第一金属线上沉积通孔光致抗蚀剂层，并蚀刻通孔光致抗蚀剂层中的通孔。第一金属线的第一导电材料暴露在通孔的底壁处。第二导电材料的通孔插入到通孔中，并且通孔插头与第一金属线形成导电路径。然后去除通孔光致抗蚀剂层，使得通孔塞的任何侧壁暴露。然后将第一扩散阻挡层沉积到通孔塞的第二导电材料的任何暴露的表面上。然后将通孔绝缘层旋涂以包围通孔塞，并且沟槽绝缘层也沉积在通孔绝缘层上。然后在具有第一扩散阻挡层的通孔上蚀刻沟槽，并且具有第一扩散阻挡层的通孔插塞作为沟槽底壁的一部分暴露。然后将第二扩散阻挡层沉积在沟槽的壁上，并且将第三导电材料沉积到沟槽中以形成第二金属线。第二金属线与通孔塞的第二导电材料形成导电路径。因此，本发明避免了在使用通孔插塞填充通孔之前在通孔绝缘层中的通孔中沉积扩散阻挡层的现有技术方法。利用本发明，可以有效地形成具有高纵横比的通孔，扩散阻挡层有效地围绕过孔塞。

33. 发明授权

US6033982A Scaled interconnect anodization for high frequency applications 有权
标题翻译：适用于高频应用的扩展互连阳极氧化
公开(公告)号：US6033982A
公开(公告)日：2000-03-07
申请号：US149208
申请日：1998-09-08
申请人： Sergey Lopatin , Robin Cheung
发明人： Sergey Lopatin , Robin Cheung
IPC分类号： H01L21/316 , H01L21/768 , H01L21/302 , H01L21/306 , H01L21/3205 , H01L21/326
CPC分类号： H01L21/76888 , H01L21/31687 , H01L21/76885 , Y10S257/915 , Y10S428/901 , Y10T428/12493 , Y10T428/12597 , Y10T428/12611
摘要： A method of forming a conductive line structure is provided. An adhesion layer is formed on a substrate surface. A seed layer is formed on the adhesion layer. A conductor is formed on the seed layer to form a partially complete structure. The partially complete structure is exposed to an electrolyte and undergoes an anodization process. At least a portion of the seed layer and a portion of the conductor are transformed to seed layer metal oxide and conductor metal oxide, respectively. At least a portion of the adhesion layer is transformed to an adhesion layer metal oxide and a further portion of the conductor is transformed to the conductor metal oxide. An outer metal layer is formed over the seed layer metal oxide and the conductor metal oxide.
摘要翻译：提供一种形成导线结构的方法。在基板表面上形成粘合层。种子层形成在粘合层上。在种子层上形成导体以形成部分完整的结构。部分完整的结构暴露于电解质并进行阳极氧化处理。种子层和导体的一部分的至少一部分分别转化为晶种层金属氧化物和导体金属氧化物。粘合层的至少一部分被转化为粘合层金属氧化物，并且导体的另一部分转变为导体金属氧化物。在种子层金属氧化物和导体金属氧化物上形成外部金属层。

34. 发明授权

US5757104A Method of operating an ultransonic piezoelectric transducer and circuit arrangement for performing the method 失效
标题翻译：操作超音速压电换能器和执行该方法的电路装置的方法
公开(公告)号：US5757104A
公开(公告)日：1998-05-26
申请号：US906130
申请日：1997-08-05
申请人： Igor Getman , Sergey Lopatin
发明人： Igor Getman , Sergey Lopatin
IPC分类号： H04R1/24 , B06B1/02 , B06B1/06 , H03H9/13 , H03H9/145 , H03H9/54 , H04R3/00 , H04R17/00 , H01L41/08
CPC分类号： B06B1/0662 , B06B1/0207 , B06B1/0692 , H03H9/132 , H03H9/545
摘要： An ultrasonic piezoelectric transducer is alternatingly operated in a transmitting mode and in a receiving mode. In the transmitting mode an electrical excitation signal is applied between one or more common electrodes and one or more transmission electrodes, and in the receiving mode an electrical reception signal is collected between the one or more common electrodes and one or more reception electrodes. Moreover, in the receiving mode one or more electrodes which are not used as reception electrodes are connected via a low impedance connection with the one or more common electrodes which has the effect that in the receiving mode the resonance frequencies of the piezoelectric transducer are shifted to lower values so that with the same operating frequency the piezolectric transducer is in series resonance in the transmitting mode and in parallel resonance in the receiving mode. In this way, the piezoelectric transducer operates under optimum conditions with perfect frequency matching both for transmission and for reception.
摘要翻译：超声波压电换能器在发射模式和接收模式下交替地操作。在发送模式中，电激励信号施加在一个或多个公共电极和一个或多个发送电极之间，并且在接收模式中，在一个或多个公共电极和一个或多个接收电极之间收集电接收信号。此外，在接收模式中，未被用作接收电极的一个或多个电极通过与一个或多个公共电极的低阻抗连接而连接，这些公共电极具有以下效果：在接收模式中，压电换能器的谐振频率转移到较低的值使得在相同的工作频率下，压电换能器在发射模式下处于串联谐振，在接收模式下处于并联谐振。以这种方式，压电换能器在最佳条件下工作，具有完美的频率匹配以用于传输和接收。

35. 发明申请

US20080132082A1 PRECISION PRINTING ELECTROPLATING THROUGH PLATING MASK ON A SOLAR CELL SUBSTRATE 失效
标题翻译：精密印刷通过太阳能电池基板上的电镀掩模进行电镀
公开(公告)号：US20080132082A1
公开(公告)日：2008-06-05
申请号：US11566205
申请日：2006-12-01
申请人： Sergey Lopatin , John O. Dukovic , David Eaglesham , Nicolay Y. Kovarsky , Robert Bachrach , John Busch , Charles Gay
发明人： Sergey Lopatin , John O. Dukovic , David Eaglesham , Nicolay Y. Kovarsky , Robert Bachrach , John Busch , Charles Gay
IPC分类号： H01L21/469 , B05C13/02
CPC分类号： H01L31/022425 , H01L31/02008 , Y02E10/50
摘要： Embodiments of the invention contemplate the formation of a low cost solar cell using a novel electroplating apparatus and method to form a metal contact structure having metal lines formed using an electrochemical plating process. The apparatus and methods described herein remove the need to perform the often costly processing steps of performing a mask preparation and formation steps, such as screen printing, lithographic steps and inkjet printing steps, to form a contact structure. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. It is thus desirable to form a solar cell device that has a low resistance connection that is reliable and cost effective. Therefore, one or more embodiments of the invention described herein are adapted to form a low cost and reliable interconnecting layer using an electrochemical plating process containing a common metal, such as copper. Embodiments of the invention may provide an apparatus and method of forming a solar cell device that utilizes a reusable masking device during one or more electrochemical deposition steps.
摘要翻译：本发明的实施例考虑使用新型电镀设备和方法形成低成本太阳能电池，以形成具有使用电化学电镀工艺形成的金属线的金属接触结构。本文描述的装置和方法不需要执行经常昂贵的处理步骤来执行掩模准备和形成步骤，例如丝网印刷，光刻步骤和喷墨印刷步骤，以形成接触结构。在太阳能电池器件中形成的互连的电阻极大地影响太阳能电池的效率。因此，希望形成具有可靠和成本有效的低电阻连接的太阳能电池装置。因此，本文描述的本发明的一个或多个实施例适用于使用包含普通金属（例如铜）的电化学电镀工艺形成低成本且可靠的互连层。本发明的实施例可以提供一种形成在一个或多个电化学沉积步骤期间利用可重复使用的掩模装置的太阳能电池装置的装置和方法。

36. 发明申请

US20080121276A1 SELECTIVE ELECTROLESS DEPOSITION FOR SOLAR CELLS 审中-公开
标题翻译：选择性电沉积太阳能电池
公开(公告)号：US20080121276A1
公开(公告)日：2008-05-29
申请号：US11564812
申请日：2006-11-29
申请人： Sergey Lopatin , Arulkumar Shanmugasundram , Robert Z. Bachrach , Charles Gay , David Eaglesham
发明人： Sergey Lopatin , Arulkumar Shanmugasundram , Robert Z. Bachrach , Charles Gay , David Eaglesham
IPC分类号： H01L31/00
CPC分类号： H01L31/022425 , H01L31/022433 , H01L31/02245 , Y02E10/50
摘要： A metal contact structure of a solar cell substrate includes a contact with a conductive layer or a capping layer that is formed using an electroless plating process. The contact may be disposed within a hole formed through the solar cell substrate or on a non-light-receiving surface of the solar cell substrate. The electroless plating process for the conductive layer uses a seed layer that includes an activation layer for electroless plating.
摘要翻译：太阳能电池基板的金属接触结构包括与使用无电解电镀工艺形成的导电层或覆盖层的接触。接触可以设置在通过太阳能电池基板形成的孔内或太阳能电池基板的非光接收表面上。用于导电层的化学镀处理使用包括用于无电镀的活化层的晶种层。

37. 发明授权

US06936925B1 Semiconductor device having copper lines with reduced electromigration using an electroplated interim copper-zinc alloy film on a copper surface 失效
标题翻译：具有在铜表面上使用电镀的中间铜 - 锌合金膜的具有减少的电迁移的铜线的半导体器件
公开(公告)号：US06936925B1
公开(公告)日：2005-08-30
申请号：US10626371
申请日：2003-07-23
申请人： Sergey Lopatin , Alexander H. Nickel
发明人： Sergey Lopatin , Alexander H. Nickel
IPC分类号： C25D3/58 , C25D5/18 , C25D7/12 , H01L21/288 , H01L21/768 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76846 , C25D3/58 , C25D5/18 , C25D7/123 , C25D17/001 , H01L21/2885 , H01L21/76858 , H01L21/76864 , H01L21/76873 , H01L2221/1089
摘要： The present invention relates to the semiconductor device fabrication industry. More particularly a semiconductor device, having an interim reduced-oxygen Cu—Zn alloy thin film (30) electroplated on a blanket Cu surface (20) disposed in a via (6) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin film (30); filling the via (6) with further Cu (26); annealing and planarizing the interconnect structure (35). The reduction of electromigration in copper interconnect lines (35) is achieved by decreasing the drift velocity in the copper line (35)/via (6), thereby decreasing the copper migration rate as well as the void formation rate, by using an interim conformal Cu-rich Cu—Zn alloy thin film (30) electroplated on a Cu surface (20) from a stable chemical solution, and by controlling the Zn-doping thereof, which improves also interconnect reliability and corrosion resistance.
摘要翻译：本发明涉及半导体器件制造业。更具体地说，一种半导体器件，具有通过使用电镀设备电镀Cu，Cu表面（20）上电镀在布置在通孔（6）上的铜箔表面（20）上的临时还原氧Cu-Zn合金薄膜（30））在一种独特的含有Zn和Cu盐的化学溶液，它们的络合剂，pH调节剂和表面活性剂; 并对中间电镀Cu-Zn合金薄膜进行退火; 用另外的Cu（26）填充通孔（6）; 退火和平坦化互连结构（35）。通过降低铜线（35）/通孔（6）中的漂移速度，可以实现铜互连线（35）中电迁移的减少，从而通过使用中间保形来降低铜迁移率以及空隙形成速率从稳定的化学溶液电镀在Cu表面（20）上的富Cu Cu-Zn合金薄膜（30），并且通过控制其Zn掺杂，这也提高了互连可靠性和耐腐蚀性。

38. 发明申请

US20050124158A1 Silver under-layers for electroless cobalt alloys 有权
标题翻译：无电钴合金的银层
公开(公告)号：US20050124158A1
公开(公告)日：2005-06-09
申请号：US10967101
申请日：2004-10-15
申请人： Sergey Lopatin , Arulkumar Shanmugasundrum , Yosef Shacham-Diamand
发明人： Sergey Lopatin , Arulkumar Shanmugasundrum , Yosef Shacham-Diamand
IPC分类号： C23C18/50 , H01L21/288 , H01L21/44 , H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76846 , C23C18/50 , C23C28/021 , C23C28/023 , H01L21/288 , H01L21/76849 , H01L21/76852 , H01L21/76874
摘要： In one embodiment, a method for depositing a capping layer on a substrate surface containing a copper layer is provided which includes exposing the substrate surface to a zinc solution to form a zinc layer on the copper layer. The method further includes exposing the substrate surface to a silver solution to form a silver layer on the zinc layer, and depositing the capping layer on the silver layer by an electroless deposition process. A second silver layer may be formed on the capping layer, if desired. In another embodiment, a composition of a deposition solution to deposit a cobalt tungsten alloy is disclosed. The deposition solution includes CaWO4, a cobalt source in a range from about 50 mM to about 500 mM, a complexing agent in a range from about 100 mM to about 700 mM and a buffering agent in a range from about 50 mM to about 500 mM.
摘要翻译：在一个实施例中，提供了一种用于在包含铜层的衬底表面上沉积覆盖层的方法，其包括将衬底表面暴露于锌溶液以在铜层上形成锌层。该方法还包括将衬底表面暴露于银溶液以在锌层上形成银层，并通过无电沉积工艺将覆盖层沉积在银层上。如果需要，可以在覆盖层上形成第二银层。在另一个实施方案中，公开了沉积钴钨合金的沉积溶液的组合物。沉积溶液包括CaWO 4 SO 4，钴源在约50mM至约500mM的范围内，络合剂在约100mM至约700mM的范围内，缓冲剂的范围约50mM至约500mM。

39. 发明授权

US06689689B1 Selective deposition process for allowing damascene-type Cu interconnect lines 有权
标题翻译：选择性沉积工艺允许镶嵌型Cu互连线
公开(公告)号：US06689689B1
公开(公告)日：2004-02-10
申请号：US09477821
申请日：2000-01-05
申请人： Paul R. Besser , Darrell M. Erb , Sergey Lopatin
发明人： Paul R. Besser , Darrell M. Erb , Sergey Lopatin
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L21/76849 , H01L21/76867 , H01L21/76888
摘要： The reliability and electromigration resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer with at least one alloying element for the metal of the feature, and then uniformly diffusing at least a minimum amount of the at least one alloying element of the at least one thin layer for a predetermined minimum depth below the upper surface of the features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer. The invention finds particular utility in “back-end” metallization processing of high-density integrated circuit semiconductor devices having sub-micron dimensioned metallization features.
摘要翻译：通过包括在金属化特征的平坦化的上表面上选择性地沉积至少一个具有至少一个合金元素的薄层的方法来增强例如铜的平坦化在线金属化图案（例如铜）的可靠性和电迁移阻力，金属的特征，然后将至少一个薄层的至少一种合金元素的至少最少量均匀地扩散到特征的上表面下方的预定最小深度以实现与其的合金化。金属化特征的合金化部分有利地减少了电迁移。通过CMP，可以在扩散/合金化之后进行平面化，以去除至少一个薄层的任何剩余的升高，合金化或非合金化部分。本发明特别适用于具有亚微米尺寸金属化特征的高密度集成电路半导体器件的“后端”金属化处理。

40. 发明授权

US06660633B1 Method of reducing electromigration in a copper line by electroplating an interim copper-zinc alloy thin film on a copper surface and a semiconductor device thereby formed 有权
标题翻译：通过在铜表面上电镀临时铜 - 锌合金薄膜和由此形成的半导体器件来减少铜线中的电迁移的方法
公开(公告)号：US06660633B1
公开(公告)日：2003-12-09
申请号：US10083809
申请日：2002-02-26
申请人： Sergey Lopatin , Alexander H. Nickel
发明人： Sergey Lopatin , Alexander H. Nickel
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , C25D3/58 , C25D5/18 , C25D7/123 , C25D17/001 , H01L21/2885 , H01L21/76858 , H01L21/76864 , H01L21/76873 , H01L2221/1089
摘要： A method of fabricating a semiconductor device, having an interim reduced-oxygen Cu-Zn alloy thin film (30) electroplated on a blanket Cu surface (20) disposed in a via (6) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin film (30); filling the via (6) with further Cu (26); annealing and planarizing the interconnect structure (35); and a semiconductor device thereby formed. The reduction of electromigration in copper interconnect lines (35) is achieved by decreasing the drift velocity in the copper line (35)/via (6), thereby decreasing the copper migration rate as well as the void formation rate, by using an interim conformal Cu-rich Cu—Zn alloy thin film (30) electroplated on a Cu surface (20) from a stable chemical solution, and by controlling the Zn-doping thereof, which improves also interconnect reliability and corrosion resistance.
摘要翻译：一种制造半导体器件的方法，其具有通过使用电镀设备通过电镀设置在通孔（6）中的铜箔表面（20）上电镀的临时还原氧Cu-Zn合金薄膜，所述Cu表面（20）在独特的含有Zn和Cu盐的化学溶液，它们的络合剂，pH调节剂和表面活性剂; 并对中间电镀Cu-Zn合金薄膜进行退火; 用另外的Cu（26）填充通孔（6）; 退火和平坦化互连结构（35）; 并由此形成半导体器件。通过降低铜线（35）/通孔（6）中的漂移速度，可以实现铜互连线（35）中电迁移的减少，从而通过使用中间保形来降低铜迁移率以及空隙形成速率从稳定的化学溶液电镀在Cu表面（20）上的富Cu Cu-Zn合金薄膜（30），并且通过控制其Zn掺杂，这也提高了互连可靠性和耐腐蚀性。

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