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31. 发明授权

US08022464B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08022464B2
公开(公告)日：2011-09-20
申请号：US12506566
申请日：2009-07-21
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/764 , H01L27/11521 , H01L29/42336 , H01L29/66825
摘要： This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the semiconductor substrate along a first direction and a second direction orthogonal to the first direction with certain spaces in each directions, a plurality of charge accumulation layers formed on the plurality of tunnel insulator films, respectively, a plurality of element isolation regions formed on the semiconductor substrate, the plurality of element isolation regions including a plurality of trenches formed along the first direction between the plurality of tunnel insulator films, a plurality of element isolation films filled in the plurality of trenches, a plurality of inter poly insulator films formed over the plurality of element isolation regions and on the upper surface and side surfaces of the plurality of charge accumulation layer along the second direction in a stripe shape, a plurality of air gaps formed between the plurality of element isolation films filled in the plurality of trenches and the plurality of inter poly insulator films and a plurality of control gate electrodes formed on the plurality of inter poly insulator films.
摘要翻译：该半导体存储器件包括半导体衬底，沿着第一方向形成在半导体衬底上的多个隧道绝缘膜，和在每个方向上具有一定间隔的与第一方向正交的第二方向，多个电荷累积层形成在多个分别形成在所述半导体衬底上的多个元件隔离区域，所述多个元件隔离区域包括在所述多个隧道绝缘膜之间沿着所述第一方向形成的多个沟槽，多个元件隔离膜填充在所述多个沟槽中，形成在所述多个元件隔离区域上并且沿着所述第二方向的所述多个电荷蓄积层的上表面和侧表面处于条形状的多个多晶硅绝缘膜，多个气隙形成在多个元件隔离膜之间填充在所述多个沟槽和所述多个多晶硅绝缘膜中，以及形成在所述多个多晶硅绝缘膜上的多个控制栅电极。

32. 发明授权

US07982244B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07982244B2
公开(公告)日：2011-07-19
申请号：US12553496
申请日：2009-09-03
申请人： Atsuhiro Sato , Hiroyuki Nitta , Fumitaka Arai
发明人： Atsuhiro Sato , Hiroyuki Nitta , Fumitaka Arai
IPC分类号： H01L29/68 , H01L29/417 , H01L27/105
CPC分类号： H01L27/11524 , H01L21/76816 , H01L27/11521
摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.
摘要翻译：半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

33. 发明申请

US20110069542A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING NAND-TYPE FLASH MEMORY AND THE LIKE 有权
标题翻译：非易失性半导体存储器件，包括NAND型闪存和类似器件
公开(公告)号：US20110069542A1
公开(公告)日：2011-03-24
申请号：US12955621
申请日：2010-11-29
申请人： Atsuhiro SATO , Keiji Shuto , Fumitaka Arai
发明人： Atsuhiro SATO , Keiji Shuto , Fumitaka Arai
IPC分类号： G11C16/26
CPC分类号： G11C16/3418 , G11C11/5642 , G11C16/0483 , G11C2211/5642
摘要： A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
摘要翻译：非易失性半导体存储器件设置有存储单元阵列，判断电位校正电路和读出电路。在存储单元阵列中，以矩阵形式布置多个存储单元，并且阵列包括作为读出对象的第一存储单元和与第一存储单元相邻设置的第二存储单元。判定电位校正电路根据第二存储单元的阈值校正判定电位。读出电路通过使用校正的判断电位读出作为读出对象的第一存储单元。

34. 发明申请

US20100176435A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100176435A1
公开(公告)日：2010-07-15
申请号：US12565181
申请日：2009-09-23
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11529
摘要： First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode.
摘要翻译：存储单元晶体管的第一栅电极在半导体衬底上彼此串联形成。第一选择晶体管的第二栅电极与第一电极的一端相邻地形成。第二选择晶体管的第三栅电极与第二电极相邻地形成。在基板上形成周边晶体管的第四栅电极。第一，第二和第三侧壁膜分别形成在第二，第三和第四栅电极的侧表面上。第三侧壁膜的膜厚大于第一和第二侧壁膜的膜厚。第一电极和第二电极之间的空间大于第一电极之间的空间，并且第二电极和第三电极之间的间隔大于第一电极和第二电极之间的间隔。

35. 发明申请

US20090129158A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING NAND-TYPE FLASH MEMORY AND THE LIKE 有权
标题翻译：非易失性半导体存储器件，包括NAND型闪存和类似器件
公开(公告)号：US20090129158A1
公开(公告)日：2009-05-21
申请号：US12354946
申请日：2009-01-16
申请人： Atsuhiro SATO , Keiji Shuto , Fumitaka Arai
发明人： Atsuhiro SATO , Keiji Shuto , Fumitaka Arai
IPC分类号： G11C16/06 , G11C5/02
CPC分类号： G11C16/3418 , G11C11/5642 , G11C16/0483 , G11C2211/5642
摘要： A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.
摘要翻译：非易失性半导体存储器件设置有存储单元阵列，判断电位校正电路和读出电路。在存储单元阵列中，以矩阵形式布置多个存储单元，并且阵列包括作为读出对象的第一存储单元和与第一存储单元相邻设置的第二存储单元。判定电位校正电路根据第二存储单元的阈值校正判定电位。读出电路通过使用校正的判断电位读出作为读出对象的第一存储单元。

36. 发明申请

US20090052242A1 NAND TYPE NONVOLATILE SEMICONDUCTOR MEMORY 审中-公开
标题翻译： NAND型非易失性半导体存储器
公开(公告)号：US20090052242A1
公开(公告)日：2009-02-26
申请号：US12194655
申请日：2008-08-20
申请人： Hideto Takekida , Atsuhiro Sato , Fumitaka Arai
发明人： Hideto Takekida , Atsuhiro Sato , Fumitaka Arai
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/10
摘要： A memory includes n-numbered memory cells (n is an integer of not less than 3) and a driver which applies a first voltage to a control gate electrode of a selected first memory cell in the n-numbered memory cells, applies a second voltage lower than the first voltage to a control gate electrode of a second memory cell adjacent to the first memory cell, and applies a third voltage lower than the second voltage to control gate electrodes of third memory cells other than the first and second memory cells at the time of programming. The first, second and third voltages have values not less than a value for turning on the n-numbered memory cells regardless of their threshold voltages.
摘要翻译：存储器包括n编号的存储单元（n是不小于3的整数）和向第n个存储单元中的所选择的第一存储单元的控制栅电极施加第一电压的驱动器，施加第二电压低于与第一存储单元相邻的第二存储单元的控制栅电极的第一电压，并施加比第二电压低的第三电压，以控制第一存储单元以外的第三存储单元的栅电极编程时间。第一，第二和第三电压具有不小于用于接通n个存储单元的值，不管其阈值电压如何。

37. 发明申请

US20060281244A1 Nonvolatile semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20060281244A1
公开(公告)日：2006-12-14
申请号：US11447941
申请日：2006-06-07
申请人： Masayuki Ichige , Fumitaka Arai , Atsuhiro Sato
发明人： Masayuki Ichige , Fumitaka Arai , Atsuhiro Sato
IPC分类号： H01L21/8238 , H01L29/94
CPC分类号： H01L29/7883 , H01L27/11521 , H01L27/11524 , H01L29/40114 , H01L29/42324 , H01L29/66825
摘要： A semiconductor memory device includes a semiconductor substrate. Two diffusion layers are separately arranged along a first direction on the surface of the semiconductor substrate and include impurities. Two element separation layers are separately arranged along a second direction in a surface of the semiconductor substrate and define an element region. A first insulating layer is disposed on the substrate. A first conductive layer is disposed on the first insulating layer between the two diffusion layers and between the two element separation layers. A second conductive layer is disposed on the first conductive layer and is smaller than the first conductive layer in the first direction and the second direction. A second insulating layer is disposed on the second conductive layer. A third conductive layer is disposed on the second insulating layer.
摘要翻译：半导体存储器件包括半导体衬底。两个扩散层沿着第一方向在半导体衬底的表面上分开排列并且包括杂质。两个元件分离层在半导体衬底的表面中沿着第二方向分开布置并且限定元件区域。第一绝缘层设置在基板上。第一导电层设置在两个扩散层之间和两个元件分离层之间的第一绝缘层上。第二导电层设置在第一导电层上，并且在第一方向和第二方向上小于第一导电层。第二绝缘层设置在第二导电层上。第三导电层设置在第二绝缘层上。

38. 发明授权

US08581325B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08581325B2
公开(公告)日：2013-11-12
申请号：US13412802
申请日：2012-03-06
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/764 , H01L27/11521 , H01L29/42336 , H01L29/66825
摘要： This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the substrate along a first direction and a second direction orthogonal to the first direction, a plurality of charge accumulation layers formed on the tunnel insulator films, respectively, a plurality of element isolation regions formed on the substrate, the element isolation regions including a plurality of trenches formed along the first direction between the tunnel insulator films, a plurality of element isolation films filled in the trenches, a plurality of inter-poly insulator films formed over the element isolation regions and on the upper and side surfaces of the charge accumulation layers along the second direction in a stripe shape, a plurality of air gaps formed between the element isolation films filled in the trenches and the inter-poly insulator films and a plurality of control gate electrodes formed on the inter-poly insulator films.
摘要翻译：该半导体存储器件包括半导体衬底，沿着第一方向和与第一方向正交的第二方向形成在衬底上的多个隧道绝缘膜，分别形成在隧道绝缘膜上的多个电荷累积层，多个形成在衬底上的元件隔离区域，元件隔离区域包括在隧道绝缘膜之间沿着第一方向形成的多个沟槽，填充在沟槽中的多个元件隔离膜，多个多晶硅绝缘膜，形成在多个绝缘膜之上所述元件隔离区域和沿着所述第二方向的所述电荷累积层的上表面和所述侧表面处于条形状，在填充在所述沟槽中的元件隔离膜和所述多晶硅绝缘膜之间形成的多个气隙和多个的多晶硅绝缘膜上形成的控制栅电极。

39. 发明申请

US20120217567A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120217567A1
公开(公告)日：2012-08-30
申请号：US13412802
申请日：2012-03-06
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/764 , H01L27/11521 , H01L29/42336 , H01L29/66825
摘要： This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the substrate along a first direction and a second direction orthogonal to the first direction, a plurality of charge accumulation layers formed on the tunnel insulator films, respectively, a plurality of element isolation regions formed on the substrate, the element isolation regions including a plurality of trenches formed along the first direction between the tunnel insulator films, a plurality of element isolation films filled in the trenches, a plurality of inter-poly insulator films formed over the element isolation regions and on the upper and side surfaces of the charge accumulation layers along the second direction in a stripe shape, a plurality of air gaps formed between the element isolation films filled in the trenches and the inter-poly insulator films and a plurality of control gate electrodes formed on the inter-poly insulator films.
摘要翻译：该半导体存储器件包括半导体衬底，沿着第一方向和与第一方向正交的第二方向形成在衬底上的多个隧道绝缘膜，分别形成在隧道绝缘膜上的多个电荷累积层，多个形成在衬底上的元件隔离区域，元件隔离区域包括在隧道绝缘膜之间沿着第一方向形成的多个沟槽，填充在沟槽中的多个元件隔离膜，多个多晶硅绝缘膜，形成在多个绝缘膜之上所述元件隔离区域和沿着所述第二方向的所述电荷累积层的上表面和所述侧表面处于条形状，在填充在所述沟槽中的元件隔离膜和所述多晶硅绝缘膜之间形成的多个气隙和多个的多晶硅绝缘膜上形成的控制栅电极。

40. 发明授权

US08158479B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08158479B2
公开(公告)日：2012-04-17
申请号：US13211394
申请日：2011-08-17
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/764 , H01L27/11521 , H01L29/42336 , H01L29/66825
摘要： This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the semiconductor substrate along a first direction and a second direction orthogonal to the first direction with certain spaces in each directions, a plurality of charge accumulation layers formed on the plurality of tunnel insulator films, respectively, a plurality of element isolation regions formed on the semiconductor substrate, the plurality of element isolation regions including a plurality of trenches formed along the first direction between the plurality of tunnel insulator films, a plurality of element isolation films filled in the plurality of trenches, a plurality of inter poly insulator films formed over the plurality of element isolation regions and on the upper surface and side surfaces of the plurality of charge accumulation layer along the second direction in a stripe shape, a plurality of air gaps formed between the plurality of element isolation films filled in the plurality of trenches and the plurality of inter poly insulator films and a plurality of control gate electrodes formed on the plurality of inter poly insulator films.
摘要翻译：该半导体存储器件包括半导体衬底，沿着第一方向形成在半导体衬底上的多个隧道绝缘膜，和在每个方向上具有一定间隔的与第一方向正交的第二方向，多个电荷累积层形成在多个分别形成在所述半导体衬底上的多个元件隔离区域，所述多个元件隔离区域包括在所述多个隧道绝缘膜之间沿着所述第一方向形成的多个沟槽，多个元件隔离膜填充在所述多个沟槽中，形成在所述多个元件隔离区域上并且沿着所述第二方向的所述多个电荷蓄积层的上表面和侧表面处于条形状的多个多晶硅绝缘膜，多个气隙形成在多个元件隔离膜之间填充在所述多个沟槽和所述多个多晶硅绝缘膜中，以及形成在所述多个多晶硅绝缘膜上的多个控制栅电极。

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