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31. 发明申请

US20050243848A1 Fair round robin scheduler for network systems 有权
标题翻译：公平的循环调度器网络系统
公开(公告)号：US20050243848A1
公开(公告)日：2005-11-03
申请号：US11027283
申请日：2004-12-31
申请人： Xin Yuan , Zhenhai Duan
发明人： Xin Yuan , Zhenhai Duan
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L47/623 , H04L47/50 , H04L47/527
摘要： A scheduler for use in a computer network system which provides an order 1 level of complexity, while maintaining proportional fairness and a constant normalized worst-case fair index to create short term and long-term fairness among backlogged flows. The scheduler utilizes an intra-class scheduling algorithm to obtain the benefits of a round robin scheduler and an inter-class scheduling algorithm to obtain the benefits of timestamp based scheduler.
摘要翻译：一种在计算机网络系统中使用的调度器，其提供1级复杂度，同时保持比例公平性和恒定的归一化最差情况公平指数，以在积压流之间创建短期和长期公平性。调度器利用类内调度算法来获得循环调度器和类间调度算法的优点，以获得基于时间戳的调度器的优点。

32. 发明授权

US08464189B2 Technology migration for integrated circuits with radical design restrictions 失效
标题翻译：具有激进设计限制的集成电路的技术迁移
公开(公告)号：US08464189B2
公开(公告)日：2013-06-11
申请号：US12726413
申请日：2010-03-18
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。本发明实现了解决RDR要求的最小布局扰动方法。本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

33. 发明授权

US08302062B2 Methods to obtain a feasible integer solution in a hierarchical circuit layout optimization 有权
标题翻译：在分层电路布局优化中获得可行整数解的方法
公开(公告)号：US08302062B2
公开(公告)日：2012-10-30
申请号：US12712880
申请日：2010-02-25
申请人： Michael S. Gray , Xiaoping Tang , Xin Yuan
发明人： Michael S. Gray , Xiaoping Tang , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. Variables are then clustered, and at least one variable from each cluster is rounded to an integer value according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
摘要翻译：描述了在分层电路布局优化中获得可行整数解的方法。在一个实施例中，接收分级电路布局和接地规则文件作为输入。分层电路布局中的约束被表示为原始的整数线性规划问题。通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。解决了松弛的线性规划问题，以获得线性规划解决方案。然后将变量进行聚类，根据线性规划解决方案，每个集群中至少有一个变量将四舍五入为整数值。接下来，确定所有变量是否四舍五入为整数值。通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。

34. 发明申请

US20100185997A1 TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 失效
标题翻译：用于具有放射性设计限制的集成电路的技术移动
公开(公告)号：US20100185997A1
公开(公告)日：2010-07-22
申请号：US12726413
申请日：2010-03-18
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。本发明实现了解决RDR要求的最小布局扰动方法。本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

35. 发明授权

US07761818B2 Obtaining a feasible integer solution in a hierarchical circuit layout optimization 失效
标题翻译：在分层电路布局优化中获得可行的整数解
公开(公告)号：US07761818B2
公开(公告)日：2010-07-20
申请号：US11782706
申请日：2007-07-25
申请人： Michael S. Gray , Xiaoping Tang , Xin Yuan
发明人： Michael S. Gray , Xiaoping Tang , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. A subset of variables from the relaxed linear programming problem is rounded to integer values according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
摘要翻译：描述了在分层电路布局优化中获得可行整数解的方法。在一个实施例中，接收分级电路布局和接地规则文件作为输入。分层电路布局中的约束被表示为原始的整数线性规划问题。通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。解决了松弛的线性规划问题，以获得线性规划解决方案。来自松弛线性规划问题的变量子集根据线性规划解决方案舍入为整数值。接下来，确定所有变量是否四舍五入为整数值。通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。

36. 发明申请

US20100153892A1 METHODS TO OBTAIN A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION 有权
标题翻译：在分层电路布局优化中获得可行整数解的方法
公开(公告)号：US20100153892A1
公开(公告)日：2010-06-17
申请号：US12712880
申请日：2010-02-25
申请人： Michael S. Gray , Xiaoping Tang , Xin Yuan
发明人： Michael S. Gray , Xiaoping Tang , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. Variables are then clustered, and at least one variable from each cluster is rounded to an integer value according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
摘要翻译：描述了在分层电路布局优化中获得可行整数解的方法。在一个实施例中，接收分级电路布局和接地规则文件作为输入。分层电路布局中的约束被表示为原始的整数线性规划问题。通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。解决了松弛的线性规划问题，以获得线性规划解决方案。然后将变量进行聚类，根据线性规划解决方案，每个集群中至少有一个变量将四舍五入为整数值。接下来，确定所有变量是否四舍五入为整数值。通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。

37. 发明授权

US07610565B2 Technology migration for integrated circuits with radical design restrictions 失效
标题翻译：具有激进设计限制的集成电路的技术迁移
公开(公告)号：US07610565B2
公开(公告)日：2009-10-27
申请号：US11697798
申请日：2007-04-09
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。另外，一种用于将集成电路设计从没有RDR的源技术迁移到具有RDR的目标技术的方法，系统和程序产品，其中可以保留用于后期插入特征的空间，并且首先在初始压实方向上发生迁移具有较差的基本规则。

38. 发明申请

US20090203012A1 Metabolic Syndrome Genetics 审中-公开
标题翻译：代谢综合征遗传学
公开(公告)号：US20090203012A1
公开(公告)日：2009-08-13
申请号：US12336769
申请日：2008-12-17
申请人： Vincent Mooser , Dawn Waterworth , KiJoung Song , Xin Yuan , Christopher W. Knouff
发明人： Vincent Mooser , Dawn Waterworth , KiJoung Song , Xin Yuan , Christopher W. Knouff
IPC分类号： C12Q1/68 , C12Q1/48
CPC分类号： C12Q1/485 , C12Q1/6883 , C12Q2600/136 , C12Q2600/156 , G01N2800/04 , G01N2800/50
摘要： A gene (and polymorphisms within it) was associated with multiple components of the metabolic syndrome. Methods of screening subjects to identify risk of metabolic syndrome and related conditions are described, as are methods of screening compounds to identify those that act on the gene product as a target for the treatment of these conditions.
摘要翻译：基因（及其内的多态性）与代谢综合征的多个成分相关。描述了筛选受试者识别代谢综合征风险和相关病症的方法，以及筛选化合物以鉴定那些作为基因产物作为治疗这些病症的靶标的方法。

39. 发明授权

US07568173B2 Independent migration of hierarchical designs with methods of finding and fixing opens during migration 失效
标题翻译：在迁移过程中，分层设计的独立迁移与查找和修复方法打开
公开(公告)号：US07568173B2
公开(公告)日：2009-07-28
申请号：US11762832
申请日：2007-06-14
申请人： Veit Gernhoefer , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Stephen L. Runyon , Leon J. Sigal , Robert F. Walker , Pieter J. Woeltgens , Xiaoyun K. Wu , Xin Yuan
发明人： Veit Gernhoefer , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Stephen L. Runyon , Leon J. Sigal , Robert F. Walker , Pieter J. Woeltgens , Xiaoyun K. Wu , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element involved in the interface strategy; migrating the base cell independently with respect to the macro based on the interface strategy; initially scaling the macro; swapping the migrated base cell into the macro; and legalizing content of the initially scaled macro.
摘要翻译：公开了独立迁移分层设计的方法。一种用于迁移集成电路中的宏的方法，包括：确定宏中的基本单元与宏之间的接口策略，所述基本单元包括接口策略中涉及的接口元素; 基于接口策略相对于宏独立地移动基站; 最初缩放宏; 将迁移的基本单元交换到宏中; 并使初始缩放的宏的内容合法化。

40. 发明申请

US20090037851A1 CONTEXT AWARE SUB-CIRCUIT LAYOUT MODIFICATION 失效
标题翻译：背景知识子电路布局修改
公开(公告)号：US20090037851A1
公开(公告)日：2009-02-05
申请号：US11831998
申请日：2007-08-01
申请人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker , Xin Yuan
发明人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are defined, minimizing a number of contexts for the sub-circuit by combining contexts into at least one stage; placing each stage into a staged layout; and modifying the sub-circuit by modifying the staged layout.
摘要翻译：公开了一种用于上下文感知子电路布局修改的方法，系统和程序产品。该方法可以包括为使用子电路的每个电路定义用于子电路的至少一个上下文; 在定义多个上下文的情况下，通过将上下文合并到至少一个级中来最小化子电路的上下文数量; 将每个阶段放置在分阶段布局中; 并通过修改分段布局修改子电路。

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