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    • 31. 发明申请
    • PROGRAMMABLE HIGH-SPEED INTERFACE
    • 可编程高速接口
    • US20100045349A1
    • 2010-02-25
    • US12539606
    • 2009-08-11
    • Bonnie I. WangChiakang SungJoseph HuangKhai NguyenPhilip Pan
    • Bonnie I. WangChiakang SungJoseph HuangKhai NguyenPhilip Pan
    • H03K3/00
    • H03K19/17744H03K19/0175H03K19/017509H03K19/017581H03K19/1774H03K19/17788
    • Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
    • 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入,高速输出,低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路,并取消选择其他电路。 高速输入和输出电路相对简单,在一个示例中,仅具有用于控制线输入的清除信号,并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活,例如具有预置,使能和清除作为控制线路输入,并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的,使得输入输出结构根据应用的要求在速度和功能之间进行优化。
    • 33. 发明授权
    • Dynamic termination-impedance control for bidirectional I/O pins
    • 用于双向I / O引脚的动态终端阻抗控制
    • US08854078B1
    • 2014-10-07
    • US13223989
    • 2011-09-01
    • Xiaobao WangBonnie I. WangChiakang SungKhai Q. Nguyen
    • Xiaobao WangBonnie I. WangChiakang SungKhai Q. Nguyen
    • H03K17/16
    • H04L25/0298H04L25/0278
    • Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.
    • 用于动态控制源和端接阻抗的电路,方法和装置。 一个输出级在发送时提供串联终止,并在接收数据时提供并行终止。 当输出级将引脚从低电压拉到高电平时,上拉器件的标称阻抗为50欧姆,而当引脚从高电压拉出时,下拉器件的标称阻抗为50欧姆 到低电压。 上拉和下拉设备在接收数据时都打开。 由于其非线性电流 - 电压特性,当引脚电压高于电源电压的一半时,上拉器件显示为50欧姆,而当引脚电压低于50欧姆时,下拉器件显示为50欧姆 电源电压的一半。 可以校准上拉和下拉器件以提供标称的50欧姆阻抗。
    • 34. 发明授权
    • Dynamic termination-impedance control for bidirectional I/O pins
    • 用于双向I / O引脚的动态终端阻抗控制
    • US08022723B1
    • 2011-09-20
    • US11458675
    • 2006-07-19
    • Xiaobao WangBonnie I. WangChiakang SungKhai Q. Nguyen
    • Xiaobao WangBonnie I. WangChiakang SungKhai Q. Nguyen
    • H03K17/16
    • H04L25/0298H04L25/0278
    • Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.
    • 用于动态控制源和端接阻抗的电路,方法和装置。 一个输出级在发送时提供串联终止,并在接收数据时提供并行终止。 当输出级将引脚从低电压拉到高电平时,上拉器件的标称阻抗为50欧姆,而当引脚从高电压拉出时,下拉器件的标称阻抗为50欧姆 到低电压。 上拉和下拉设备在接收数据时都打开。 由于其非线性电流 - 电压特性,当引脚电压高于电源电压的一半时,上拉器件显示为50欧姆,而当引脚电压低于50欧姆时,下拉器件显示为50欧姆 电源电压的一半。 可以校准上拉和下拉器件以提供标称的50欧姆阻抗。
    • 39. 发明授权
    • Programmable high speed I/O interface
    • 可编程高速I / O接口
    • US06825698B2
    • 2004-11-30
    • US10229342
    • 2002-08-26
    • Bonnie I. WangChiakang SungJoseph HuangKhai NguyenPhilip Pan
    • Bonnie I. WangChiakang SungJoseph HuangKhai NguyenPhilip Pan
    • H03B100
    • H03K19/17744H03K19/0175H03K19/017509H03K19/017581H03K19/1774H03K19/17788
    • Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
    • 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入,高速输出,低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路,并取消选择其他电路。 高速输入和输出电路相当简单,在一个示例中,仅具有用于控制线路输入的清除信号,并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活,例如具有预置,使能和清除作为控制线路输入,并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的,使得输入输出结构根据应用的要求在速度和功能之间进行优化。