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31. 发明申请

US20100128154A1 SYSTEMS AND METHODS TO PROVIDE REFERENCE CURRENT WITH NEGATIVE TEMPERATURE COEFFICIENT 有权
标题翻译：使用负温度系数提供参考电流的系统和方法
公开(公告)号：US20100128154A1
公开(公告)日：2010-05-27
申请号：US12323802
申请日：2008-11-26
申请人： Chen Xu , Yaowu Mo
发明人： Chen Xu , Yaowu Mo
IPC分类号： H04N5/335 , G05F3/16
CPC分类号： H04N5/357 , G05F1/561 , G05F3/30
摘要： Systems and methods for providing one or more reference currents with respective negative temperature coefficients are provided. A first voltage is divided to provide a divided voltage, which is compared to a reference voltage (e.g., a bandgap reference voltage) to provide a control voltage. The first voltage and the one or more reference currents are based on the control voltage.
摘要翻译：提供了用于提供具有相应的负温度系数的一个或多个参考电流的系统和方法。第一电压被分压以提供分压，其与参考电压（例如，带隙参考电压）进行比较以提供控制电压。第一电压和一个或多个参考电流基于控制电压。

32. 发明授权

US07675093B2 Antiblooming imaging apparatus, system, and methods 有权
标题翻译：抗皱成像设备，系统和方法
公开(公告)号：US07675093B2
公开(公告)日：2010-03-09
申请号：US11605103
申请日：2006-11-28
申请人： Chen Xu , Gennadiy Agranov , Igor Karasev
发明人： Chen Xu , Gennadiy Agranov , Igor Karasev
IPC分类号： H01L27/148
CPC分类号： H04N5/378 , H04N5/3594 , H04N5/3745
摘要： Apparatus, systems and methods are described to assist in reducing dark current in an active pixel sensor. A potential barrier arrangement is configured to block the flow of charge carriers generated outside a photosensitive region. In various embodiments, a potential well-potential barrier arrangement is formed to direct charge carriers away from the photosensitive region during an integration time.
摘要翻译：描述了装置，系统和方法以帮助减少有源像素传感器中的暗电流。势垒布置被配置为阻挡在感光区域外产生的电荷载流子的流动。在各种实施例中，形成势阱势垒布置，以在积分时间期间使电荷载流子远离光敏区域。

33. 发明申请

US20090316466A1 METHOD, APPARATUS AND SYSTEM, PROVIDING A ONE-TIME PROGRAMMABLE MEMORY DEVICE 有权
标题翻译：方法，装置和系统，提供一次性可编程存储器件
公开(公告)号：US20090316466A1
公开(公告)日：2009-12-24
申请号：US12545892
申请日：2009-08-24
申请人： Chen Xu , Thomas W. Voshell , Karl Holtzclaw
发明人： Chen Xu , Thomas W. Voshell , Karl Holtzclaw
IPC分类号： G11C17/00 , G11C7/00
CPC分类号： G11C17/16 , G11C17/18
摘要： Disclosed are apparatus, system and methods of programming and readout of a one-time programmable memory devise having an array of memory cells, where the cells include an anti-fuse element and an in-cell amplifier transistor. Circuitry configured for programming and correlated double sampling readout of the cells is also disclosed.
摘要翻译：公开了具有存储器单元阵列的一次性可编程存储器设备的编程和读出的装置，系统和方法，其中单元包括反熔丝元件和单元内放大器晶体管。还公开了配置用于单元的编程和相关双采样读出的电路。

34. 发明申请

US20090145764A1 COMPOSITE COATINGS FOR WHISKER REDUCTION 审中-公开
公开(公告)号：US20090145764A1
公开(公告)日：2009-06-11
申请号：US11953936
申请日：2007-12-11
申请人： Joseph A. Abys , Jingye Li , Edward J. Kudrak, JR. , Chen Xu
发明人： Joseph A. Abys , Jingye Li , Edward J. Kudrak, JR. , Chen Xu
IPC分类号： C25D15/00
CPC分类号： C25D15/02 , C25D3/30
摘要： There is provided a method and composition for applying a wear resistant composite coating onto a metal surface of an electrical component. The method comprises contacting the metal surface with an electrolytic plating composition comprising (a) a source of tin ions and (b) non-metallic particles, and applying an external source of electrons to the electrolytic plating composition to thereby electrolytically deposit the composite coating onto the metal surface, wherein the composite coating comprises tin metal and the non-metallic particles.

35. 发明申请

US20050249969A1 Preserving solderability and inhibiting whisker growth in tin surfaces of electronic components 审中-公开
标题翻译：保持电子部件锡表面的可焊性和抑制晶须生长
公开(公告)号：US20050249969A1
公开(公告)日：2005-11-10
申请号：US10968500
申请日：2004-10-19
申请人： Chen Xu , Yun Zhang , Chonglun Fan , Oscar Khaselev , Joseph Abys , Eric Walch , Marlies Kleinfeld , Hans Eckert
发明人： Chen Xu , Yun Zhang , Chonglun Fan , Oscar Khaselev , Joseph Abys , Eric Walch , Marlies Kleinfeld , Hans Eckert
IPC分类号： B32B15/01 , C25D5/10 , C25D5/12 , H01G4/228 , H01L23/495
CPC分类号： H01G4/228 , B32B15/01 , C25D5/12 , H01L23/49582 , H01L24/48 , H01L24/49 , H01L2224/48247 , H01L2224/49171 , H01L2924/00014 , H01L2924/01078 , H01L2924/01327 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/19041 , Y10T428/12715 , Y10T428/12722 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A method for reducing whisker formation and preserving solderability in tin coatings over metal features of electronic components. The tin coating has internal tensile stress and is between about 0.5 μm and about 4.0 μm in thickness. There is a nickel-phosphorus layer under the tin coating.
摘要翻译：一种减少电子部件的金属特征的方法，用于减少锡涂层中的晶须形成和保持锡涂层的可焊性。锡涂层具有内部拉伸应力，厚度在约0.5μm至约4.0μm之间。在锡涂层下面有一个镍 - 磷层。

36. 发明授权

US06517893B2 Method of manufacture of printed wiring boards having multi-purpose finish 有权
标题翻译：具有多功能面漆的印刷电路板的制造方法
公开(公告)号：US06517893B2
公开(公告)日：2003-02-11
申请号：US09941086
申请日：2001-08-28
申请人： Joseph A. Abys , Chonglun Fan , Brian T. Smith , Bruce F. Stacy , Chen Xu
发明人： Joseph A. Abys , Chonglun Fan , Brian T. Smith , Bruce F. Stacy , Chen Xu
IPC分类号： B05D512
CPC分类号： H05K3/244 , H01L24/81 , H01L24/85 , H01L2224/81444 , H01L2224/85444 , H01L2924/00014 , H05K3/062 , H05K3/108 , H05K3/28 , H05K3/384 , H05K2203/0571 , Y10T29/49144 , Y10T29/49149 , Y10T29/49155 , Y10T428/12528 , Y10T428/1275 , Y10T428/12875 , Y10T428/12882 , Y10T428/1291 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A printed wiring board (PWB) and a method of manufacturing the same. In one embodiment, the PWB includes: (1) a substrate having a conductive trace located thereon and (2) a multi-purpose finish including palladium alloy where palladium is alloyed with cobalt or a platinum group metal and is located on at least a portion of the conductive trace, which forms both a non-contact finish and a contact finish for the PWB.
摘要翻译：印刷电路板（PWB）及其制造方法。在一个实施例中，PWB包括：（1）具有位于其上的导电迹线的基底和（2）包含钯合金的多用途涂饰，其中钯与钴或铂族金属合金并且位于至少一部分上的导电迹线，其形成用于PWB的非接触光洁度和接触光洁度。

37. 发明授权

US08829767B2 Large-scale fabrication of vertically aligned ZnO nanowire arrays 有权
标题翻译：垂直排列的ZnO纳米线阵列的大规模制造
公开(公告)号：US08829767B2
公开(公告)日：2014-09-09
申请号：US13473867
申请日：2012-05-17
申请人： Zhong Lin Wang , Youfan Hu , Yan Zhang , Chen Xu , Guang Zhu
发明人： Zhong Lin Wang , Youfan Hu , Yan Zhang , Chen Xu , Guang Zhu
IPC分类号： H01L41/113 , H02N2/18 , B82Y30/00 , B82Y5/00 , H01L27/20 , B82Y40/00 , H01L41/319
CPC分类号： H02N2/18 , B82Y5/00 , B82Y30/00 , B82Y40/00 , H01L27/20 , H01L41/113 , H01L41/317 , H01L41/319 , H02N2/181 , H02N2/186
摘要： A generator includes a substrate, a first electrode layer, a dense plurality of vertically-aligned piezoelectric elongated nanostructures, an insulating layer and a second electrode layer. The substrate has a top surface and the first electrode layer is disposed on the top surface of the substrate. The dense plurality of vertically-aligned piezoelectric elongated nanostructures extends from the first electrode layer. Each of the nanostructures has a top end. The insulating layer is disposed on the top ends of the nanostructures. The second electrode layer is disposed on the non-conductive layer and is spaced apart from the nanostructures.
摘要翻译：发电机包括衬底，第一电极层，密集多个垂直排列的压电细长纳米结构，绝缘层和第二电极层。衬底具有顶表面，并且第一电极层设置在衬底的顶表面上。密集的多个垂直排列的压电细长纳米结构从第一电极层延伸。每个纳米结构具有顶端。绝缘层设置在纳米结构的顶端。第二电极层设置在非导电层上并与纳米结构间隔开。

38. 发明授权

US08793630B2 Clock tree planning for an ASIC 有权
标题翻译： ASIC的时钟树规划
公开(公告)号：US08793630B2
公开(公告)日：2014-07-29
申请号：US13478272
申请日：2012-05-23
申请人： Liang Ge , Suoming Pu , Chen Xu , Bo Yu
发明人： Liang Ge , Suoming Pu , Chen Xu , Bo Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62
摘要： The present invention discloses a method and system for clock tree planning for an ASIC, the method comprising: determining a netlist and a timing constraint file of the ASIC; creating a sequential device undirected graph for sequential devices in the netlist according to connection relationships of the sequential devices in the netlist and timing constraint relationships of the sequential devices in the timing constraint file; grouping the sequential devices in the netlist according to the sequential device undirected graph, such that the sequential devices in one group do not have a timing constraint relationship with the sequential devices in another group. The ASIC design method improved by using this method will reduce the design cycle from weeks to days, and enable designer to quickly plan the clock tree, thus reducing the design time and improving the design efficiency.
摘要翻译：本发明公开了一种用于ASIC的时钟树规划方法和系统，所述方法包括：确定所述ASIC的网表和定时约束文件; 根据网表中的顺序设备的连接关系和时序约束文件中的顺序设备的时序约束关系，为网表中的顺序设备创建顺序设备无向图; 根据顺序设备无向图对网表中的顺序设备进行分组，使得一组中的顺序设备不具有与另一组中的顺序设备的时序约束关系。通过使用这种方法改进的ASIC设计方法可以将设计周期从几周缩短到几天，使设计人员能够快速规划时钟树，从而缩短设计时间，提高设计效率。

39. 发明授权

US08643750B2 Reducing noise in image sensors by concurrently reading reset and image signal levels from active and reference pixels 有权
标题翻译：通过同时从有源和参考像素读取复位和图像信号电平，从而降低图像传感器中的噪声
公开(公告)号：US08643750B2
公开(公告)日：2014-02-04
申请号：US12930015
申请日：2010-12-22
申请人： Yaowu Mo , Chen Xu
发明人： Yaowu Mo , Chen Xu
IPC分类号： H04N5/217 , H04N5/235
CPC分类号： H04N5/3575 , H04N5/2176 , H04N5/365
摘要： A method of one aspect includes reading a reset level of an active pixel, and concurrently, reading a reset level of a reference pixel. The method also includes reading an image signal level of the active pixel, and concurrently, reading an image signal level of the reference pixel. A reduced noise image signal level of the active pixel is generated based on the reset levels and the image signal levels of the active and reference pixels. Other methods are disclosed as well as apparatus and systems.
摘要翻译：一个方面的方法包括读取有源像素的复位电平，同时读取参考像素的复位电平。该方法还包括读取有源像素的图像信号电平，同时读取参考像素的图像信号电平。基于有效和参考像素的复位电平和图像信号电平，生成有源像素的降低噪声图像信号电平。公开了其它方法以及装置和系统。

40. 发明授权

US08623451B2 Large-scale lateral nanowire arrays nanogenerators 有权
标题翻译：大型横向纳米线阵列纳米发生器
公开(公告)号：US08623451B2
公开(公告)日：2014-01-07
申请号：US12943499
申请日：2010-11-10
申请人： Zhong L. Wang , Chen Xu , Yong Qin , Guang Zhu , Rusen Yang , Youfan Hu , Yan Zhang
发明人： Zhong L. Wang , Chen Xu , Yong Qin , Guang Zhu , Rusen Yang , Youfan Hu , Yan Zhang
IPC分类号： B05D5/12 , H01L41/22 , H01L41/00 , H04R17/00 , H02N2/00
CPC分类号： H01L41/316 , H02N2/18
摘要： In a method of making a generating device, a plurality of spaced apart elongated seed members are deposited onto a surface of a flexible non-conductive substrate. An elongated conductive layer is applied to a top surface and a first side of each seed member, thereby leaving an exposed second side opposite the first side. A plurality of elongated piezoelectric nanostructures is grown laterally from the second side of each seed layer. A second conductive material is deposited onto the substrate adjacent each elongated first conductive layer so as to be coupled the distal end of each of the plurality of elongated piezoelectric nanostructures. The second conductive material is selected so as to form a Schottky barrier between the second conductive material and the distal end of each of the plurality of elongated piezoelectric nanostructures and so as to form an electrical contact with the first conductive layer.
摘要翻译：在制造发生装置的方法中，多个间隔开的细长种子构件沉积在柔性非导电基底的表面上。将细长的导电层施加到每个种子构件的顶表面和第一侧，从而留下与第一侧相对的暴露的第二侧。多个细长的压电纳米结构从每个种子层的第二侧横向生长。第二导电材料沉积在每个细长的第一导电层上的衬底上，以便耦合到多个细长压电纳米结构中的每一个的远端。选择第二导电材料以在第二导电材料和多个细长压电纳米结构中的每一个的远端之间形成肖特基势垒，并且与第一导电层形成电接触。

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