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31. 发明授权

US08299520B2 Semiconductor devices including auxiliary gate electrodes and methods of fabricating the same 有权
标题翻译：包括辅助栅电极的半导体器件及其制造方法
公开(公告)号：US08299520B2
公开(公告)日：2012-10-30
申请号：US12544631
申请日：2009-08-20
申请人： Suk-pil Kim , Yoon-dong Park , Jae-young Choi , June-mo Koo , Byung-hee Hong
发明人： Suk-pil Kim , Yoon-dong Park , Jae-young Choi , June-mo Koo , Byung-hee Hong
IPC分类号： H01L29/66 , H01L29/788 , G11C16/04
CPC分类号： H01L29/66833 , B82Y10/00 , G11C16/0483 , H01L27/11521 , H01L27/11568 , H01L27/12 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： According to some embodiments, a semiconductor device includes first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode is provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes are configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.
摘要翻译：根据一些实施例，半导体器件包括第一和第二辅助栅电极以及与第一和第二辅助栅电极交叉的半导体层。主栅电极设置在半导体层上，使得半导体层位于主栅电极和第一和第二辅助栅电极之间。此外，第一和第二辅助栅电极被配置为在半导体层中诱发相应的第一和第二场效应源极/漏极区。还讨论了相关方法。

32. 发明申请

US20090261314A1 Non-volatile memory device and method of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20090261314A1
公开(公告)日：2009-10-22
申请号：US12232745
申请日：2008-09-23
申请人： Suk-pil Kim , Yoon-dong Park , June-mo Koo
发明人： Suk-pil Kim , Yoon-dong Park , June-mo Koo
IPC分类号： H01L45/00
CPC分类号： H01L27/249 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146
摘要： Provided are a non-volatile memory device that may be configured in a stacked structure and may be more easily highly integrated, and a method of fabricating the non-volatile memory device. At least one first electrode and at least one second electrode are provided. The at least one second electrode may cross the at least one first electrode. At least one data storage layer may be at an intersection between the at least one first electrode and the at least one second electrode. Any one of the at least one first electrode and the at least one second electrode may include at least one junction diode connected to the at least one data storage layer.
摘要翻译：提供了可以被配置为堆叠结构并且可以更容易地高度集成的非易失性存储器件，以及制造非易失性存储器件的方法。提供至少一个第一电极和至少一个第二电极。所述至少一个第二电极可以穿过所述至少一个第一电极。至少一个数据存储层可以在至少一个第一电极和至少一个第二电极之间的交叉点处。所述至少一个第一电极和所述至少一个第二电极中的任何一个可以包括连接到所述至少一个数据存储层的至少一个结二极管。

33. 发明申请

US20080242011A1 Method of fabricating non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20080242011A1
公开(公告)日：2008-10-02
申请号：US11978567
申请日：2007-10-30
申请人： Seung-hwan Song , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Jae-woong Hyun , Choong-ho Lee , Tae-hun Kim
发明人： Seung-hwan Song , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Jae-woong Hyun , Choong-ho Lee , Tae-hun Kim
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on the plurality of lower charge storing layers. A plurality of upper charge storing layers may be formed on a top surface of the semiconductor layer. A plurality of upper control gate electrodes may be formed on the plurality of upper charge storing layers, wherein the plurality of lower and upper control gate electrodes may be arranged alternately.
摘要翻译：根据示例性实施例的制造非易失性存储器件的方法可包括在衬底上形成半导体层。多个下电荷存储层可以形成在半导体层的底表面上。可以在多个下电荷存储层上形成多个下控制栅电极。多个上电荷存储层可以形成在半导体层的顶表面上。多个上部控制栅极电极可以形成在多个上部电荷存储层上，其中多个下部和上部控制栅电极可以交替布置。

34. 发明授权

US07948024B2 Multi-layered, vertically stacked non-volatile memory device and method of fabrication 有权
标题翻译：多层垂直堆叠的非易失性存储器件和制造方法
公开(公告)号：US07948024B2
公开(公告)日：2011-05-24
申请号：US12484339
申请日：2009-06-15
申请人： Suk-pil Kim , Yoon-dong Park , June-mo Koo , Tae-eung Yoon
发明人： Suk-pil Kim , Yoon-dong Park , June-mo Koo , Tae-eung Yoon
IPC分类号： H01L21/336
CPC分类号： H01L27/11556 , H01L27/11521 , H01L27/11551 , H01L27/11578
摘要： A nonvolatile memory device is provided that includes; a first semiconductor layer extending in a first direction, a second semiconductor layer extending in parallel with and separated from the first semiconductor layer, an isolation layer between the first semiconductor layer and second semiconductor layer, a first control gate electrode between the first semiconductor layer and the isolation layer, a second control gate electrode between the second semiconductor layer and the isolation layer, wherein the second control gate electrode and first control gate electrode are respectively disposed at opposite sides of the isolation layer, a first charge storing layer between the first control gate electrode and the first semiconductor layer, and a second charge storing layer between the second control gate electrode and the second semiconductor layer.
摘要翻译：提供了一种非易失性存储装置，包括：沿第一方向延伸的第一半导体层，与第一半导体层平行延伸并与第一半导体层分离的第二半导体层，在第一半导体层和第二半导体层之间的隔离层，第一半导体层与第一半导体层之间的第一半导体层，所述隔离层，所述第二半导体层和所述隔离层之间的第二控制栅极电极，其中所述第二控制栅极电极和所述第一控制栅电极分别设置在所述隔离层的相对侧，所述第一控制栅极之间的第一电荷存储层栅电极和第一半导体层，以及在第二控制栅电极和第二半导体层之间的第二电荷存储层。

35. 发明申请

US20070012974A1 Method for manufacturing material layer, method for manufacturing ferroelectric capacitor using the same, ferroelectric capacitor manufactured by the same method, semiconductor memory device having ferroelectric capacitor and manufacturing method thereof 审中-公开
标题翻译：用于制造材料层的方法，使用该方法制造铁电电容器的方法，通过相同方法制造的铁电电容器，具有铁电电容器的半导体存储器件及其制造方法
公开(公告)号：US20070012974A1
公开(公告)日：2007-01-18
申请号：US11484582
申请日：2006-07-12
申请人： June-mo Koo , Bum-seok Seo , Young-soo Park , Jung-hyun Lee , Sang-min Shin , Suk-pil Kim
发明人： June-mo Koo , Bum-seok Seo , Young-soo Park , Jung-hyun Lee , Sang-min Shin , Suk-pil Kim
IPC分类号： H01L29/94
CPC分类号： H01L21/02197 , H01L21/0228 , H01L21/31691 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： Provided is a method for manufacturing a material layer capable of increasing the deposition rate of a noble metal layer on a ferroelectric layer, a method for manufacturing a ferroelectric capacitor using the same, a ferroelectric capacitor manufactured by the same method, and a semiconductor memory device having the ferroelectric capacitor and a manufacturing method thereof. According to a method for manufacturing the material layer, a ferroelectric layer is formed. The ferroelectric layer may be exposed to seed plasma, and a material layer including a source material of the seed plasma may be formed on a region of the ferroelectric layer exposed to the seed plasma.
摘要翻译：提供一种能够提高强电介质层上的贵金属层的沉积速度的材料层的制造方法，使用该材料的铁电电容器的制造方法，通过相同的方法制造的铁电电容器以及半导体存储器件具有铁电电容器及其制造方法。根据材料层的制造方法，形成铁电体层。可以将铁电层暴露于种子等离子体，并且可以在暴露于种子等离子体的铁电层的区域上形成包括种子等离子体的源材料的材料层。

36. 发明申请

US20060022236A1 Ferroelectric capacitor and ferroelectric memory with Ir-Ru alloy electrode and method of manufacturing the same 有权
公开(公告)号：US20060022236A1
公开(公告)日：2006-02-02
申请号：US10978795
申请日：2004-11-02
申请人： Sang-min Shin , Suk-pil Kim , Young-soo Park , Jung-hyun Lee , June-mo Koo
发明人： Sang-min Shin , Suk-pil Kim , Young-soo Park , Jung-hyun Lee , June-mo Koo
IPC分类号： H01L29/76
CPC分类号： H01L27/11502 , H01L28/55 , H01L28/65 , Y10T29/417
摘要： A ferroelectric capacitor comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer. A ferroelectric memory comprises a substrate and a plurality of memory cells arranged on the substrate. Each memory cell comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer.

37. 发明申请

US20090321878A1 NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20090321878A1
公开(公告)日：2009-12-31
申请号：US12366151
申请日：2009-02-05
申请人： June-mo Koo , Suk-pil Kim , Tae-Eung Yoon
发明人： June-mo Koo , Suk-pil Kim , Tae-Eung Yoon
IPC分类号： H01L29/8605
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146
摘要： Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second electrode.
摘要翻译：提供了可以以堆叠结构进行扩展并因此可以高度集成的非易失性存储器件，以及制造非易失性存储器件的方法。所述非易失性存储器件包括：至少一个第一电极，至少一个第二电极，与所述至少一个第一电极交叉，至少一个数据存储层插入在所述至少一个第一电极和所述第二电极之间的区域中所述至少一个第一电极与所述至少一个第二电极交叉，并且所述至少一个金属硅化物层插入在所述至少一个第一电极和所述至少一个第二电极之间，所述至少一个第一电极在所述至少一个第一电极与至少一个第二电极。

38. 发明申请

US20060090702A1 Duplex chemical vapor deposition system and pulsed processing method using the same 审中-公开
标题翻译：双相化学气相沉积系统和使用其的脉冲处理方法
公开(公告)号：US20060090702A1
公开(公告)日：2006-05-04
申请号：US11185689
申请日：2005-07-21
申请人： June-mo Koo , Young-soo Park , Sang-min Shin , Suk-pil Kim
发明人： June-mo Koo , Young-soo Park , Sang-min Shin , Suk-pil Kim
IPC分类号： C23C16/00
CPC分类号： C23C16/409 , C23C16/44
摘要： Embodiments are provided of a duplex chemical vapor deposition (CVD) system and pulsed processing method using the same. The duplex CVD system may include first and second process chambers, one or more reactive sources, and reactive source suppliers that correspond to the reactive sources, respectively. The reactive source suppliers may include a first conduit portion connected to the respective reactive sources, a second conduit portion having one terminal connected to the first conduit portion and the other terminal connected to the first process chamber, and a third conduit portion having one terminal connected to the first conduit portion and the other terminal connected to the second process chamber.
摘要翻译：提供了双相化学气相沉积（CVD）系统和使用其的脉冲处理方法的实施例。双相CVD系统可以分别包括对应于无源电源的第一和第二处理室，一个或多个无源电源和无源电源供应器。反应源供应商可以包括连接到各个反应源的第一管道部分，具有连接到第一管道部分的一个端子和连接到第一处理室的另一个端子的第二管道部分，以及一个端子连接的第三管道部分连接到第二处理室的第一管道部分和另一个端子。

39. 发明申请

US20060001070A1 Capacitor of a memory device and fabrication method thereof 失效
标题翻译：存储器件的电容器及其制造方法
公开(公告)号：US20060001070A1
公开(公告)日：2006-01-05
申请号：US11120184
申请日：2005-05-03
申请人： Young-soo Park , Jung-hyun Lee , Choong-rae Cho , June-mo Koo , Suk-pil Kim , Sang-min Shin
发明人： Young-soo Park , Jung-hyun Lee , Choong-rae Cho , June-mo Koo , Suk-pil Kim , Sang-min Shin
IPC分类号： H01L21/00 , H01L27/108
CPC分类号： H01L28/91 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： A capacitor of a memory device, and a method of fabricating the same, includes a lower electrode electrically coupled to a doping region of a transistor structure, the lower electrode having a metal electrode and a metal oxide electrode, a ferroelectric layer covering and extending laterally along the lower electrode, and an upper electrode formed on the ferroelectric layer.
摘要翻译：存储器件的电容器及其制造方法包括电耦合到晶体管结构的掺杂区域的下电极，下电极具有金属电极和金属氧化物电极，铁电层覆盖并横向延伸沿着下电极和形成在铁电层上的上电极。

40. 发明授权

US07910967B2 Ferroelectric capacitor having three-dimensional structure, nonvolatile memory device having the same and method of fabricating the same 失效
标题翻译：具有三维结构的铁电电容器，具有相同的非易失性存储器件及其制造方法
公开(公告)号：US07910967B2
公开(公告)日：2011-03-22
申请号：US11515024
申请日：2006-09-05
申请人： Sang-min Shin , Young-soo Park , June-mo Koo , Byoung-jae Bae , I-hun Song , Suk-pil Kim
发明人： Sang-min Shin , Young-soo Park , June-mo Koo , Byoung-jae Bae , I-hun Song , Suk-pil Kim
IPC分类号： H01L21/00 , H01L31/112 , H01L23/48
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A ferroelectric capacitor having a three-dimensional structure, a nonvolatile memory device having the same, and a method of fabricating the same are provided. The ferroelectric capacitor may include a trench-type lower electrode, at least one layer formed around the lower electrode, a ferroelectric layer (PZT layer) formed on the lower electrode and the at least one layer and an upper electrode formed on the ferroelectric layer. The at least one layer may be at least one insulating interlayer and the at least one layer may also be at least one diffusion barrier layer. The at least one layer may be formed of an insulating material excluding SiO2 or may have a perovskite crystal structure excluding Pb.
摘要翻译：提供具有三维结构的铁电电容器，具有其的非易失性存储器件及其制造方法。铁电电容器可以包括沟槽型下电极，形成在下电极周围的至少一层，形成在下电极和至少一层上的铁电层（PZT层）和形成在铁电层上的上电极。所述至少一个层可以是至少一个绝缘夹层，并且所述至少一个层也可以是至少一个扩散阻挡层。所述至少一层可以由除了SiO2之外的绝缘材料形成，或者可以具有不包括Pb的钙钛矿晶体结构。

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