会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 33. 发明申请
    • Semiconductor device having recess and planarized layers
    • 具有凹槽和平坦化层的半导体器件
    • US20060115987A1
    • 2006-06-01
    • US11331573
    • 2006-01-13
    • Trung DoanTyler Lowrey
    • Trung DoanTyler Lowrey
    • H01L21/461
    • H01L29/66825H01L21/28273H01L27/115H01L27/11521H01L29/42324H01L29/42336H01L29/7881
    • A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.
    • 提供了一种用于形成诸如电可擦除可编程只读存储器的浮置栅极半导体器件的方法。 该器件包括具有电隔离的有源区的硅衬底。 栅极氧化物以及FET的其它部件(例如,源极,漏极)形成在有源区域中。 通过将导电层(例如多晶硅)沉积到栅极氧化物上而形成自对准浮栅。 然后将导电层化学机械平面化到隔离层的端点,使得去除凹部中和栅极氧化物上的材料以外的所有导电层。 在形成浮栅之后,在浮栅上形成绝缘层,在绝缘层上形成控制栅。