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31. 发明申请

US20140014966A1 GALLIUM NITRIDE DEVICES HAVING LOW OHMIC CONTACT RESISTANCE 有权
标题翻译：具有低OHMIC接触电阻的氮化镓器件
公开(公告)号：US20140014966A1
公开(公告)日：2014-01-16
申请号：US13548305
申请日：2012-07-13
申请人： Kamal Tabatabaie , William E. Hoke , Eduardo M. Chumbes , Kevin McCarthy
发明人： Kamal Tabatabaie , William E. Hoke , Eduardo M. Chumbes , Kevin McCarthy
IPC分类号： H01L29/20 , H01L29/778
CPC分类号： H01L29/66462 , H01L29/0657 , H01L29/0843 , H01L29/2003 , H01L29/201 , H01L29/7787 , H01L29/7789
摘要： A semiconductor structure having mesa structure comprising: a lower semiconductor layer; an upper semiconductor layer having a higher band gap than, and in direct contact with, the lower semiconductor layer to form a two-dimension electron gas (2DEG) region between the upper semiconductor layer. The 2DEG region has outer edges terminating at sidewalls of the mesa. An additional electron donor layer has a band gap higher than the band gap of the lower layer disposed on sidewall portions of the mesa structure and on the region of the 2DEG region terminating at sidewalls of the mesa. An ohmic contact material is disposed on the electron donor layer. In effect, a sideway HEMT is formed with the electron donor layer, the 2DEG region and the ohmic contact material increasing the concentration of electrons (i.e., lowering ohmic contact resistance) all along the contact between the lower semiconductor layer and the electron donor layer.
摘要翻译：一种具有台面结构的半导体结构，包括：下半导体层; 上半导体层具有比下半导体层更高的带隙并且与下半导体层直接接触以在上半导体层之间形成二维电子气（2DEG）区。 2DEG区域具有终止于台面侧壁的外边缘。另外的电子供体层具有高于设置在台面结构的侧壁部分上的下层的带隙和在台面的侧壁处终止的2DEG区域的区域的带隙。欧姆接触材料设置在电子供体层上。实际上，沿着下半导体层和电子供体层之间的接触，形成有电子供体层，2DEG区和欧姆接触材料增加电子浓度（即降低欧姆接触电阻）的侧面HEMT。

32. 发明申请

US20120300168A1 OPTICALLY TRANSPARENT CONDUCTORS 审中-公开
标题翻译：光学透明导体
公开(公告)号：US20120300168A1
公开(公告)日：2012-11-29
申请号：US13113838
申请日：2011-05-23
申请人： William E. Hoke
发明人： William E. Hoke
IPC分类号： G02F1/136 , H01L29/205
CPC分类号： G02F1/292 , G02F1/13439 , H01L29/2003 , H01L29/205
摘要： An optically transparent electrically conductive structure having: an optically transparent substrate; an optically transparent buffer and barrier layers; a plurality of optically transparent, two-dimensional electron gas (2-DEG) carrier layers disposed on the substrate. A barrier layer is disposed over a corresponding one of the carrier layers. One of the carrier layers comprises: a GaN channel layer and wherein the barrier layer is Al1-xInxN or Al5yGa1-6yInyN where 0.10
摘要翻译：一种透光导电结构，具有：光学透明基板; 光学透明的缓冲层和阻挡层; 设置在基板上的多个光学透明的二维电子气（2-DEG）载体层。阻挡层设置在相应的一个载体层上。载体层之一包括：GaN沟道层，其中阻挡层为Al1-xInxN或Al5yGa1-6yInyN，其中0.10

33. 发明申请

US20120261721A1 SEMICONDUCTOR STRUCTURES HAVING NUCLEATION LAYER TO PREVENT INTERFACIAL CHARGE FOR COLUMN III-V MATERIALS ON COLUMN IV OR COLUMN IV-IV MATERIALS 审中-公开
标题翻译：具有核化层的半导体结构，以防止IV-IV或IV-IV族材料上的III-V族III族材料的界面电荷
公开(公告)号：US20120261721A1
公开(公告)日：2012-10-18
申请号：US13088813
申请日：2011-04-18
申请人： William E. Hoke
发明人： William E. Hoke
IPC分类号： H01L29/267 , H01L21/20
CPC分类号： H01L21/02378 , H01L21/02381 , H01L21/02458 , H01L21/02543 , H01L21/02546 , H01L21/02549
摘要： A semiconductor structure having: a column IV material or column IV-IV material; a nucleation layer of AlN layer or a column III nitride having more than 60% aluminum content on a surface of the column IV material or column IV-IV material and a layer of column III-V material over the nucleation layer, where the nucleation layer and the layer of column III-V material over the nucleation layer have different crystallographic structures. In one embodiment, the column III-V nucleation layer is a nitride and the column III-V material of the over the nucleation layer is a non-nitride such as, for example, an arsenide (e.g., GaAs), a phosphide (e.g., InP), or an antimonide (e.g. InSb), or alloys thereof.
摘要翻译：具有柱IV材料或第IV-IV族材料的半导体结构; AlN层的成核层或在IV族材料或第IV-IV族材料的表面上具有超过60％的铝含量的III族氮化物，以及成核层上的III-V族材料层，其中成核层并且成核层上的III-V族材料层具有不同的晶体结构。在一个实施方案中，III-V族成核层是氮化物，并且成核层之上的III-V族材料是非氮化物，例如砷化物（例如GaAs），磷化物（例如，，InP）或锑化物（例如InSb）或其合金。

34. 发明申请

US20110049581A1 SEMICONDUCTOR STRUCTURE AND METHOD 有权
标题翻译：半导体结构与方法
公开(公告)号：US20110049581A1
公开(公告)日：2011-03-03
申请号：US12553249
申请日：2009-09-03
申请人： Eduardo M. Chumbes , William E. Hoke , Kelly P. Ip , Dale M. Shaw , Steven K. Brierley
发明人： Eduardo M. Chumbes , William E. Hoke , Kelly P. Ip , Dale M. Shaw , Steven K. Brierley
IPC分类号： H01L27/06 , H01L21/302 , H01L21/02 , H01L29/38 , H01L21/31
CPC分类号： H01L21/8252 , H01L21/31111 , H01L27/0605
摘要： A method for forming a structure on a surface of a semiconductor. The method includes: forming the material as a lower layer of the structure using a first deposition process to provide the lower layer with a first etch rate to a predetermined etchant; forming the upper layer of the structure with the material on the lower using a second deposition process to provide the upper layer with a second etch rate to the predetermined etchant higher than the first etch rate; and applying the predetermined etchant to upper layer to selectively remove the upper while leaving the lower layer.
摘要翻译：一种在半导体表面上形成结构的方法。该方法包括：使用第一沉积工艺将所述材料形成为所述结构的下层，以向所述下层提供预定蚀刻剂的第一蚀刻速率; 使用第二沉积工艺在所述下部材料上形成所述结构的上层，以向所述上层提供比所述第一蚀刻速率高的所述预定蚀刻剂的第二蚀刻速率; 并将预定的蚀刻剂施加到上层，以选择性地移除上部，同时离开下层。

35. 发明申请

US20080258135A1 SEMICONDUCTOR STRUCTURE HAVING PLURAL BACK-BARRIER LAYERS FOR IMPROVED CARRIER CONFINEMENT 审中-公开
标题翻译：具有改进的载波限制的多个反向障碍层的半导体结构
公开(公告)号：US20080258135A1
公开(公告)日：2008-10-23
申请号：US11737217
申请日：2007-04-19
申请人： William E. Hoke , Eduardo M. Chumbes
发明人： William E. Hoke , Eduardo M. Chumbes
IPC分类号： H01L29/205
CPC分类号： H01L29/7783 , H01L29/2003 , H01L29/201 , H01L29/205
摘要： A semiconductor structure having: a channel layer having a conductive channel therein; a pair of polarization generating layers; a spacer layer disposed between the pair of polarization generating layers. The polarization generating layers create polarization fields along a common, predetermined direction. Each one of the pair of polarizations layers may be InGaN; InAlGaN; or quaternary InxAlyGa1-x-yN and x is greater than or equal to y/2. The polarization generating layers create polarization fields along a common, predetermined direction constructively increasing the total polarization fields experienced by the channel layer to increase confinement of carriers in the conductive channel.
摘要翻译：一种半导体结构，具有：沟道层，其中具有导电沟道; 一对偏光产生层; 间隔层，设置在该对偏振产生层之间。极化产生层沿共同的预定方向产生极化场。该对偏振层中的每一个可以是InGaN; InAlGaN; 或四分之一以上的Al x Y y和x大于或等于y / 2。极化产生层沿着共同的预定方向产生偏振场，从而建构性地增加由沟道层所经历的总偏振场，以增加导电沟道中载流子的约束。

36. 发明授权

US06271547B1 Double recessed transistor with resistive layer 有权
标题翻译：具有电阻层的双凹槽晶体管
公开(公告)号：US06271547B1
公开(公告)日：2001-08-07
申请号：US09369954
申请日：1999-08-06
申请人： William E. Hoke , Katerina Hur , Rebecca McTaggart
发明人： William E. Hoke , Katerina Hur , Rebecca McTaggart
IPC分类号： H01L31072
CPC分类号： H01L29/66462 , H01L29/7785
摘要： A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of GaxIn1−xAs is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of GaxIn1−xAs is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of AlyIn1−yAs is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.
摘要翻译：提供晶体管结构。该结构具有源极和漏极。 GaxIn1-xAs的掺杂覆盖层设置在源电极和漏电极下方并提供盖层开口。 GaxIn1-xAs的未掺杂电阻层设置在盖层下方并且限定与盖层开口对准的电阻层，并具有第一宽度。 AlyIn1-yAs的肖特基层设置在电阻层下方。未掺杂沟道层设置在肖特基层下方。半绝缘基板设置在沟道层下方。电阻层开口下方的肖特基层的顶表面提供具有小于第一宽度的第二宽度的凹部。栅电极与由肖特基层提供的凹部的底表面接触。

37. 发明授权

US5060030A Pseudomorphic HEMT having strained compensation layer 失效
标题翻译：具有应变补偿层的假形HEMT
公开(公告)号：US5060030A
公开(公告)日：1991-10-22
申请号：US554240
申请日：1990-07-18
申请人： William E. Hoke
发明人： William E. Hoke
IPC分类号： H01L29/778
CPC分类号： H01L29/7784
摘要： A pseudomorphic high electron mobility transistor includes a substrate for supporting a semiconductor active region. The semiconductor active region includes a channel layer comprised of InGaAs, which when disposed over said substrate develops an intrinsic lattice tensile strain and charge donor layer comprised of a wide bandgap Group III-V material, said layer being arranged to donate charge to said channel layer. The HEMT further includes a strain compensating layer having an intrinsic lattice compressive strain which is disposed between said channel layer and said substrate. The strain compensating layer has a strain characteristic which compensates for the tensile strain in the channel layer permitting said channel layer to be grow thicker or with high In concentration prior to reaching its so-called critical thickness.
摘要翻译：假型高电子迁移率晶体管包括用于支撑半导体有源区的衬底。所述半导体有源区包括由InGaAs组成的沟道层，当在所述衬底上设置时，产生本征晶格拉伸应变和由宽带隙III-V族材料构成的电荷施主层，所述层被布置为向所述沟道层。 HEMT还包括具有本征晶格压缩应变的应变补偿层，其设置在所述沟道层和所述衬底之间。应变补偿层具有应变特性，其补偿通道层中的拉伸应变，允许所述通道层在达到其所谓的临界厚度之前变厚或具有高浓度。

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