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31. 发明授权

US5970346A Fuse window guard ring structure for nitride capped self aligned contact processes 失效
标题翻译：保险丝窗保护环结构，用于氮化物封盖自对准接触工艺
公开(公告)号：US5970346A
公开(公告)日：1999-10-19
申请号：US933370
申请日：1997-09-19
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L21/768 , H01L23/525 , H01L21/336
CPC分类号： H01L21/768 , H01L23/5258 , H01L2924/0002 , Y10S148/055
摘要： The present invention provides a structure and method for forming a moisture barrier guard ring structure 38 44 48 52 54 for around a fuse window 30 in a semiconductor device. The invention begins by forming a fuse structure 32 33 34 over the isolation regions cross the fuse window area. A cap layer 38 and an interlevel dielectric layer (ILD) 40 are formed over the fuse structure. A first annular ring 44 (e.g., contact w-plug) is formed over the isolation region 20 surrounding the fuse window area 30 and over the fuse structure 32 33 34. A key feature is that the first annular ring 44 and the cap layer 38 form a moisture proof seal over the fuse structure. A first conductive wiring line 48 is formed over the first annular ring 44. Next, an inter metal dielectric (IMD) layer 50 is formed over the interlevel dielectric layer 40. A second annular ring 52 is formed through the inter metal dielectric layer 50 on the first conductive wiring line 48. A second conductive wiring line 54 is formed over the second annular ring 44. A passivation layer 60 64 is formed over the resulting surface and a fuse window 31 is etched through the passivation layer 60 64 and partially through the inter metal dielectric layer 50 over the fuse window area 30. The first annular ring 44, the first conductive wiring line 48, the second annular ring 52, the second conductive wiring line 54 comprise the invention's moisture proof guard ring structure surrounding the fuse window area.
摘要翻译：本发明提供一种在半导体器件中形成保险丝窗30周围的防潮保护环结构38 44 48 52 54的结构和方法。本发明开始于在隔离区域上形成穿过保险丝窗口区域的熔丝结构32 33 34。在熔丝结构上形成覆盖层38和层间电介质层（ILD）40。第一环形环44（例如，接触插头）形成在隔离区域20周围的隔离区域20周围的保险丝窗口区域30和保险丝结构32 33 34上。关键特征是第一环形环44和盖层38 在保险丝结构上形成防潮密封。第一导电布线48形成在第一环形环44之上。接下来，在层间电介质层40之上形成金属间电介质（IMD）层50.第二环形环52穿过金属间介电层50 第一导电布线48.第二导电布线54形成在第二环形环44之上。钝化层6064形成在所得表面上方，并且熔丝窗31被蚀刻穿过钝化层60 64并且部分地穿过第一环形环44，第一导电布线48，第二环形环52，第二导电布线54包括本发明的围绕保险丝窗口区域的防潮保护环结构。

32. 发明授权

US5926706A Method for making a trench-free buried contact with low resistance on semiconductor integrated circuits 失效
标题翻译：在半导体集成电路上制造具有低电阻的无沟槽埋地接触的方法
公开(公告)号：US5926706A
公开(公告)日：1999-07-20
申请号：US835578
申请日：1997-04-09
申请人： Jhon-Jhy Liaw , Jin-Yuan Lee
发明人： Jhon-Jhy Liaw , Jin-Yuan Lee
IPC分类号： H01L21/265 , H01L21/285 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , H01L21/28512 , H01L21/26586
摘要： A method is achieved for forming buried contacts with diffused contact regions on semiconductor integrated circuits having low sheet resistance between the buried contacts and the field effect transistors. The method also allows for greater misalignment tolerances that prevent trenching or electrical opens from occurring in the diffused contact regions when etching the polycide interconnecting lines over the contacts. The method utilizes the etch back of an opening in the photoresist contact mask and a subsequent angular implant to extend the diffused contact regions to reduce the sheet resistance between the buried contacts and the FETs. The method is especially useful for electrically connecting the drain of the pass transistor to the gate of the pull-down transistor on static RAM devices.
摘要翻译：实现了在掩埋触点和场效应晶体管之间具有低薄层电阻的半导体集成电路上形成具有扩散接触区域的掩埋触点的方法。该方法还允许更大的未对准公差，其当在触点上蚀刻多晶硅互连线时，防止在扩散接触区域中发生开沟或电开路。该方法利用光致抗蚀剂接触掩模中的开口的蚀刻背面和随后的角度注入来延伸扩散接触区域，以减小掩埋触点和FET之间的薄层电阻。该方法特别适用于将静态RAM器件中的传输晶体管的漏极电连接到下拉晶体管的栅极。

33. 发明授权

US5593922A Method for buried contact isolation in SRAM devices 失效
标题翻译： SRAM器件中埋地接地隔离方法
公开(公告)号：US5593922A
公开(公告)日：1997-01-14
申请号：US660301
申请日：1996-06-07
申请人： Jhon-Jhy Liaw , Hsien W. Chin
发明人： Jhon-Jhy Liaw , Hsien W. Chin
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8244 , H01L21/44 , H01L21/60
CPC分类号： H01L21/76895 , H01L21/28 , H01L27/11 , Y10S148/02
摘要： A method for fabrication of polysilicon buried contacts is described which overcomes the problems of current leakage which occur at sub-micron spacings between these contacts. The failure of the conventional channel stop protection at these spacings is compensated for by performing the buried contact anti-punchthrough ion-implant using large-angle-tilt (LAT) implantation. This provides adequate dopant under the edge of the field oxide to eliminate excessive current leakages between buried contacts at sub-micron spacings. The method is particularly effective in the manufacture of static random access memories (SRAMs) where such sub-micron spacings occur to a large degree.
摘要翻译：描述了一种用于制造多晶硅掩埋触点的方法，其克服了在这些触点之间的亚微米间隔处发生的电流泄漏的问题。通过使用大角度倾斜（LAT）植入来执行埋入式接触反穿通离子注入来补偿在这些间隔处的常规通道停止保护的故障。这在场氧化物的边缘处提供了足够的掺杂剂，以在亚微米间隔处消除掩埋触点之间的过大的电流泄漏。该方法在制造其中这种亚微米间隔在很大程度上发生的静态随机存取存储器（SRAM）中特别有效。

34. 发明授权

US08987831B2 SRAM cells and arrays 有权
标题翻译： SRAM单元和阵列
公开(公告)号：US08987831B2
公开(公告)日：2015-03-24
申请号：US13349349
申请日：2012-01-12
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L27/11 , G11C11/412 , H01L21/8234 , H01L21/84 , H01L27/02 , H01L27/088 , H01L27/12
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/823431 , H01L21/845 , H01L27/0207 , H01L27/0886 , H01L27/1108 , H01L27/1211
摘要： Static random access memory (SRAM) cells and SRAM cell arrays are disclosed. In one embodiment, an SRAM cell includes a pull-up transistor. The pull-up transistor includes a Fin field effect transistor (FinFET) that has a fin of semiconductive material. An active region is disposed within the fin. A contact is disposed over the active region of the pull-up transistor. The contact is a slot contact that is disposed in a first direction. The active region of the pull-up transistor is disposed in a second direction. The second direction is non-perpendicular to the first direction.
摘要翻译：公开了静态随机存取存储器（SRAM）单元和SRAM单元阵列。在一个实施例中，SRAM单元包括上拉晶体管。上拉晶体管包括具有半导体材料鳍的Fin场效应晶体管（FinFET）。有源区域设置在翅片内。触点设置在上拉晶体管的有源区上。触点是沿第一方向设置的槽接触件。上拉晶体管的有源区域设置在第二方向。第二方向与第一方向非垂直。

35. 发明授权

US08952547B2 Semiconductor device with contact structure with first/second contacts formed in first/second dielectric layers and method of forming same 有权
标题翻译：具有在第一/第二电介质层中形成的具有第一/第二触点的接触结构的半导体器件及其形成方法
公开(公告)号：US08952547B2
公开(公告)日：2015-02-10
申请号：US11775039
申请日：2007-07-09
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L27/11 , H01L23/522 , H01L23/528 , H01L23/485 , H01L27/02
CPC分类号： H01L27/088 , H01L21/32115 , H01L21/768 , H01L21/76895 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L29/0649 , H01L29/66568 , H01L2924/0002 , H01L2924/00
摘要： A contact structure includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer connecting to a gate region of a MOS transistor or to a first contact. A butted contact structure abutting a source/drain region and a gate electrode includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer with one end resting on the gate electrode and the other end in contact with the first contact.
摘要翻译：接触结构包括形成在连接到MOS晶体管的源极/漏极区域的第一电介质层中的第一接触和形成在连接到MOS晶体管的栅极区域或第一接触点的第二介电层中的第二接触。邻接源极/漏极区域和栅电极的对接接触结构包括形成在连接到MOS晶体管的源极/漏极区域的第一电介质层中的第一接触和形成在第二电介质层中的第二接触，其一端静止在栅电极上，另一端与第一触点接触。

36. 发明申请

US20130258759A1 Methods and Apparatus for SRAM Cell Structure 有权
公开(公告)号：US20130258759A1
公开(公告)日：2013-10-03
申请号：US13436149
申请日：2012-03-30
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： G11C11/00 , H01L21/66
CPC分类号： H01L27/1104 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G11C11/412 , H01L27/0207 , H01L27/0924 , H01L27/11
摘要： An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second CVdd nodes, the first and second CVss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon. In another embodiment, a word line is formed and bit lines and a CVdd and a CVss line are formed overlying the SRAM cell and coupled to the corresponding ones of the nodes. Methods are disclosed for forming the cell structure.

37. 发明申请

US20130181297A1 SRAM Cells and Arrays 有权
标题翻译： SRAM单元和阵列
公开(公告)号：US20130181297A1
公开(公告)日：2013-07-18
申请号：US13349349
申请日：2012-01-12
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/823431 , H01L21/845 , H01L27/0207 , H01L27/0886 , H01L27/1108 , H01L27/1211
摘要： Static random access memory (SRAM) cells and SRAM cell arrays are disclosed. In one embodiment, an SRAM cell includes a pull-up transistor. The pull-up transistor includes a Fin field effect transistor (FinFET) that has a fin of semiconductive material. An active region is disposed within the fin. A contact is disposed over the active region of the pull-up transistor. The contact is a slot contact that is disposed in a first direction. The active region of the pull-up transistor is disposed in a second direction. The second direction is non-perpendicular to the first direction.
摘要翻译：公开了静态随机存取存储器（SRAM）单元和SRAM单元阵列。在一个实施例中，SRAM单元包括上拉晶体管。上拉晶体管包括具有半导体材料鳍的Fin场效应晶体管（FinFET）。有源区域设置在翅片内。触点设置在上拉晶体管的有源区上。触点是沿第一方向设置的槽接触件。上拉晶体管的有源区域设置在第二方向。第二方向与第一方向非垂直。

38. 发明申请

US20120149171A1 Shallow Trench Isolation with Improved Structure and Method of Forming 有权
标题翻译：浅沟槽隔离与改进的结构和形成方法
公开(公告)号：US20120149171A1
公开(公告)日：2012-06-14
申请号：US13399488
申请日：2012-02-17
申请人： Jhon-Jhy Liaw , Chao-Cheng Chen , Chia-Wei Chang
发明人： Jhon-Jhy Liaw , Chao-Cheng Chen , Chia-Wei Chang
IPC分类号： H01L21/762
CPC分类号： H01L21/823878 , H01L21/76232
摘要： A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width.
摘要翻译：公开了浅沟槽隔离（STI）结构和形成STI结构的方法。实施例是形成半导体结构的方法。该方法包括在半导体衬底中形成凹陷; 在所述凹部的侧壁上形成第一材料; 通过所述凹部的底面形成加宽的凹部; 从所述凹部的侧壁去除所述第一材料; 以及在所述凹部和所述加宽的凹部中形成介电材料。凹部的底面通过第一材料露出，凹部的底面具有第一宽度。加宽的凹部具有第二宽度。第二宽度大于第一宽度。

39. 发明授权

US08059452B2 Cell structure for dual port SRAM 有权
标题翻译：双端口SRAM的单元结构
公开(公告)号：US08059452B2
公开(公告)日：2011-11-15
申请号：US12773662
申请日：2010-05-04
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903
摘要： An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected.
摘要翻译：提供集成电路和布置集成电路的方法。集成电路包括第一和第二晶体管。第一晶体管包括包括第一源极和第一漏极的第一有源区域; 以及在所述第一有源区上方的第一栅电极。第二晶体管包括第二有源区，包括第二源极和第二漏极; 以及在所述第二有源区上方并连接到所述第一栅极的第二栅电极，其中所述第一源极和所述第二源极电连接，并且所述第一漏极和所述第二漏极电连接。

40. 发明申请

US20100213552A1 Cell Structure for Dual Port SRAM 有权
标题翻译：双端口SRAM的单元结构
公开(公告)号：US20100213552A1
公开(公告)日：2010-08-26
申请号：US12773662
申请日：2010-05-04
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L29/78
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903
摘要： An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected.
摘要翻译：提供集成电路和布置集成电路的方法。集成电路包括第一和第二晶体管。第一晶体管包括包括第一源极和第一漏极的第一有源区域; 以及在所述第一有源区上方的第一栅电极。第二晶体管包括第二有源区，包括第二源极和第二漏极; 以及在所述第二有源区上方并连接到所述第一栅极的第二栅电极，其中所述第一源极和所述第二源极电连接，并且所述第一漏极和所述第二漏极电连接。

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