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    • 31. 发明申请
    • PROCESSING RECEIVED DIGITAL DATA SIGNALS BASED ON A RECEIVED DIGITAL DATA FORMAT
    • 基于收到的数字数据格式处理接收到的数字信号
    • US20110019786A1
    • 2011-01-27
    • US12893237
    • 2010-09-29
    • Weidong Li
    • Weidong Li
    • H04B1/10
    • H04B1/406
    • An integrated circuit radio receiver includes radio frequency (“RF”) front-end circuitry to receive a wireless signal and to produce digital data. The integrated circuit radio receiver includes a baseband processor is operable to process the digital data, in which the baseband processor is operable to produce a format designation based on the digital data. The baseband processor includes a plurality of digital filtering logic in which each of the digital filtering logic includes a level of digital filtering. The baseband processor further includes logic operable to select between each digital filtering logic of the plurality of digital filtering logic based upon the format designation, and to process the digital data with the selected level of digital filtering.
    • 集成电路无线电接收机包括用于接收无线信号并产生数字数据的射频(“RF”)前端电路。 集成电路无线电接收机包括可操作以处理数字数据的基带处理器,其中基带处理器可操作以基于数字数据产生格式指定。 基带处理器包括多个数字滤波逻辑,其中每个数字滤波逻辑包括数字滤波电平。 基带处理器还包括可操作以基于格式指定在多个数字滤波逻辑的每个数字滤波逻辑之间进行选择的逻辑,并且以所选择的数字滤波电平来处理数字数据。
    • 32. 发明授权
    • Method and system for digital baseband receiver with digital RF/IF/VLIF support in GSM/GPRS/EDGE compliant handsets
    • 在符合GSM / GPRS / EDGE标准的手机中支持数字RF / IF / VLIF数字基带接收机的方法和系统
    • US07856070B2
    • 2010-12-21
    • US10929855
    • 2004-08-30
    • Weidong Li
    • Weidong Li
    • H03K9/00
    • H04L27/38H04B1/40H04L27/22
    • A method and system for digital baseband receiver with digital RF/IF/VLIF support in GSM/GPRS/EDGE compliant handsets. The method may comprise receiving an input signal which may be a digital RF signal, IF or VLIF signals, and the input signal may comprise of I and Q components. The serial digital RF signal may be converted to a parallel digital formatted signal, the latter of which may be transferred to an input of a multiplexer. The received IF signal or VLIF signal may be filtered and transferred to the input of the DU which may convert the VLIF signal to a baseband signal by processing the VLIF signal with a CORDIC algorithm. The DU may bypass processing the IF signal. The output of the DU may be transferred to the input of the multiplexer, such that the multiplexer may select the parallel digital formatted signal or the output of the DU.
    • 一种在GSM / GPRS / EDGE兼容手机中支持数字RF / IF / VLIF的数字基带接收机的方法和系统。 该方法可以包括接收可以是数字RF信号,IF或VLIF信号的输入信号,并且输入信号可以包括I和Q分量。 串行数字RF信号可以被转换成并行的数字格式化信号,后者可以被传送到多路复用器的输入端。 接收到的IF信号或VLIF信号可以被滤波并传送到DU的输入端,DU可以通过用CORDIC算法处理VLIF信号将VLIF信号转换成基带信号。 DU可能会旁路处理IF信号。 DU的输出可以被传送到多路复用器的输入,使得多路复用器可以选择并行数字格式化信号或DU的输出。
    • 33. 发明授权
    • Processing received digital data signals based on a received digital data format
    • 处理基于接收的数字数据格式接收数字数据信号
    • US07831228B2
    • 2010-11-09
    • US12267393
    • 2008-11-07
    • Weidong Li
    • Weidong Li
    • H04B7/08H04B1/18H04B1/06H04B1/10
    • H04B1/406
    • An integrated circuit radio receiver includes radio frequency (“RF”) front end circuitry for receiving and transmitting digital data received through a wireless interface. A baseband processor is operable to process the digital data received through the wireless interface. A plurality of digital filtering logic is included wherein each digital filtering logic includes a level of digital filtering based upon a received digital data signal format. The integrated circuit radio receiver includes logic that is operable to select between each digital filtering logic of the plurality of digital filtering logic based upon the received digital data signal format to process the digital data received through the wireless interface with the selected level of digital filtering.
    • 集成电路无线电接收机包括用于接收和发送通过无线接口接收的数字数据的射频(“RF”)前端电路。 基带处理器可操作以处理通过无线接口接收的数字数据。 包括多个数字滤波逻辑,其中每个数字滤波逻辑包括基于所接收的数字数据信号格式的数字滤波电平。 集成电路无线电接收机包括逻辑,其可操作以基于所接收的数字数据信号格式在多个数字滤波逻辑的每个数字滤波逻辑之间进行选择,以处理通过无线接口接收的数字数据与所选择的数字滤波电平。
    • 35. 发明授权
    • Method and system for a message processor switch for performing incremental redundancy in edge compliant terminals
    • 用于在边缘兼容终端中执行增量冗余的消息处理器交换机的方法和系统
    • US07681065B2
    • 2010-03-16
    • US10933988
    • 2004-09-03
    • Weidong Li
    • Weidong Li
    • G06F1/10
    • D04B21/14
    • Certain embodiments of the invention may be found in a method and system for processing messages. Aspects of the method may comprise receiving at least one signal on a chip that controls switching from a core processor to a DSP. At least a first bus that couples the core processor to a message processor and at least a first clock signal that clocks the core processor may be switched. At least a second bus that couples the DSP to the message processor and at least a second clock signal that clocks the DSP may be switched. When a loss of clock signal from the core processor or the DSP to the message processor is detected, a third clock signal for clocking the message processor may be generated. The message processor switch significantly reduces the amount of bandwidth utilized for transfer of data between the core processor and the DSP and provides incremental redundancy (IR) without high hardware cost and software MIPS, thereby providing significant improvement in system performance.
    • 可以在用于处理消息的方法和系统中找到本发明的某些实施例。 该方法的方面可以包括在芯片上接收控制从核心处理器到DSP的切换的至少一个信号。 可以切换将核心处理器耦合到消息处理器的至少第一总线和至少对时钟核心处理器的第一时钟信号。 可以切换将DSP耦合到消息处理器的至少第二总线和至少对时钟DSP的第二时钟信号。 当检测到从核心处理器或DSP到消息处理器的时钟信号的丢失时,可以产生用于计时消息处理器的第三时钟信号。 消息处理器交换机大大减少了用于核心处理器和DSP之间传输数据的带宽量,并提供增量冗余(IR),无需高硬件成本和软件MIPS,从而提高系统性能。
    • 37. 发明授权
    • Unique method for performing horizontal and vertical video decimation within a wireless device
    • 在无线设备内执行水平和垂直视频抽取的独特方法
    • US07365748B2
    • 2008-04-29
    • US10917006
    • 2004-08-12
    • Ruei-Shiang SuenWeidong Li
    • Ruei-Shiang SuenWeidong Li
    • G06T11/00
    • G06T3/4023G06T3/4092H04M1/72544H04W4/18H04W88/02
    • A method of presenting graphical images within a wireless terminal that includes receiving an original graphical image, having a source resolution, to be presented on a display screen. The native pixel resolution of the display screen may differ from that of the original graphical image. A complex decimation pattern when applied to the image allows the original graphical image to be resized from the source resolution of the original graphical image to a decimated resolution operable to be displayed within the native resolution of the display screen. Decimated pixels need not be further processed to reduce the processing requirements imposed on the system processor. Operations normally associated with the decimated portions of the image may be offloaded from the processing module to improve system efficiency.
    • 一种在无线终端内呈现图形图像的方法,包括接收具有源分辨率的原始图形图像以呈现在显示屏幕上。 显示屏幕的原始像素分辨率可能与原始图形图像的分辨率不同。 当应用于图像时的复杂抽取模式允许将原始图形图像从原始图形图像的源分辨率调整为可显示在显示屏幕的原始分辨率内的抽取分辨率。 抽取的像素不需要进一步处理,以减少对系统处理器的处理要求。 通常与图像的抽取部分相关联的操作可以从处理模块卸载以提高系统效率。
    • 39. 发明申请
    • Processing received digital data signals based on a received digital data format
    • 处理基于接收的数字数据格式接收数字数据信号
    • US20070135068A1
    • 2007-06-14
    • US11298431
    • 2005-12-09
    • Weidong Li
    • Weidong Li
    • H04B7/08H04B1/06
    • H04B1/406
    • An integrated circuit radio receiver includes radio frequency (“RF”) front end circuitry for receiving and transmitting digital data received through a wireless interface. A baseband processor is operable to process the digital data received through the wireless interface. A first logic is operable to provide a first level of digital filtering for a first received digital data signal format. A second logic is operable to provide the first level of digital filtering and derotation for a second received digital data signal format. A third logic is operable to provide a second level of digital filtering for a third received digital data signal format wherein the second level of digital filtering is reduced in comparison to the first level of digital filtering. Selection logic is operable to select between the first, second and third logic for processing the digital data received through the wireless interface.
    • 集成电路无线电接收机包括用于接收和发送通过无线接口接收的数字数据的射频(“RF”)前端电路。 基带处理器可操作以处理通过无线接口接收的数字数据。 第一逻辑可操作地为第一接收数字数据信号格式提供第一级数字滤波。 第二逻辑可操作地为第二接收数字数据信号格式提供第一级数字滤波和解旋。 第三逻辑可操作以为第三接收数字数据信号格式提供第二级数字滤波,其中与第一级数字滤波相比,第二级数字滤波被减少。 选择逻辑可操作以在用于处理通过无线接口接收的数字数据的第一,第二和第三逻辑之间进行选择。
    • 40. 发明申请
    • Transmission interface module for digital and continuous-waveform transmission signals
    • 传输接口模块,用于数字和连续波形传输信号
    • US20070133711A1
    • 2007-06-14
    • US11298432
    • 2005-12-09
    • Weidong Li
    • Weidong Li
    • H04L27/00
    • H04L27/0008H04B1/406
    • An integrated circuit radio transmitter includes a baseband processing module that is operable to generate digital data for transmission through a wireless interface, first transmission logic for generating first continuous waveform transmission signals, second transmission logic for generating second continuous waveform transmission signals, and third transmission logic for generating digital transmission signals. The integrated circuit radio transmitter also includes logic for selecting an output transmission signal format including at least one of the first continuous waveform transmission signals, the second continuous waveform transmission signals, and the digital transmission signals; and radio frequency (“RF”) transmission circuitry for receiving and transmitting the selected output transmission signal format.
    • 集成电路无线电发射机包括:基带处理模块,用于生成用于通过无线接口传输的数字数据;用于产生第一连续波形传输信号的第一传输逻辑;用于产生第二连续波形传输信号的第二传输逻辑;以及第三传输逻辑 用于产生数字传输信号。 集成电路无线电发射机还包括用于选择包括第一连续波形传输信号,第二连续波形传输信号和数字传输信号中的至少一个的输出传输信号格式的逻辑; 和射频(“RF”)发送电路,用于接收和发送所选择的输出发送信号格式。