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31. 发明授权

US08232593B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08232593B2
公开(公告)日：2012-07-31
申请号：US12714002
申请日：2010-02-26
申请人： Wataru Saito , Syotaro Ono , Hiroshi Ohta , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
发明人： Wataru Saito , Syotaro Ono , Hiroshi Ohta , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/407 , H01L29/7395 , H01L29/861 , H01L29/8611
摘要： A power semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first or second conductivity type, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, a third semiconductor layer of the second conductivity type selectively formed on a surface of the second semiconductor layer, at least one trench formed in a periphery of the third semiconductor layer on the surface of the second semiconductor layer, a depth of a bottom surface of the at least one trench being deeper than a bottom surface of the third semiconductor layer, and shallower than a top surface of the first semiconductor layer, and some or all of the at least one trench being in contact with a side surface of the third semiconductor layer, at least one insulator buried in the at least one trench, a first main electrode electrically connected to the first semiconductor layer, and a second main electrode electrically connected to the third semiconductor layer.
摘要翻译：根据本发明实施例的功率半导体器件包括第一或第二导电类型的第一半导体层，形成在第一半导体层上的第一导电类型的第二半导体层，第二导电类型的第三半导体层选择性地形成在第二半导体层的表面上，形成在第二半导体层的表面上的第三半导体层的周边中的至少一个沟槽，至少一个沟槽的底表面的深度比底部表面，并且比第一半导体层的顶表面浅，并且至少一个沟槽的一些或全部与第三半导体层的侧表面接触，至少一个绝缘体埋在第三半导体层至少一个沟槽，与第一半导体层电连接的第一主电极和电连接的第二主电极引导到第三半导体层。

32. 发明授权

US08159023B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08159023B2
公开(公告)日：2012-04-17
申请号：US12692527
申请日：2010-01-22
申请人： Syotaro Ono , Wataru Saito , Nana Hatano , Hiroshi Ohta , Miho Watanabe
发明人： Syotaro Ono , Wataru Saito , Nana Hatano , Hiroshi Ohta , Miho Watanabe
IPC分类号： H01L29/00
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/66712 , H01L29/7397
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type on the semiconductor substrate, and a plurality of second semiconductor regions of a second conductivity type disposed separately in the first semiconductor region. A difference between a charge quantity expressed by an integral value of a net activated doping concentration in the second semiconductor regions in the surface direction of the semiconductor substrate and a charge quantity expressed by an integral value of a net activated doping concentration in the first semiconductor region in the surface direction of the semiconductor substrate is always a positive quantity and becomes larger from the depth of the first junction plane to a depth of a second junction plane on an opposite side from the first junction plane.
摘要翻译：半导体器件包括第一导电类型的半导体衬底，半导体衬底上的第一导电类型的第一半导体区域和分开设置在第一半导体区域中的多个第二导电类型的第二半导体区域。由半导体衬底的表面方向上的第二半导体区域中的净活化掺杂浓度的积分值表示的电荷量与由第一半导体区域中的净活化掺杂浓度的积分值表示的电荷量之间的差异在半导体基板的表面方向总是为正量，并且从第一接合面的深度到与第一接合面相反的一侧的第二接合面的深度变得更大。

33. 发明授权

US08125023B2 Vertical type power semiconductor device having a super junction structure 有权
标题翻译：具有超结结构的垂直型功率半导体器件
公开(公告)号：US08125023B2
公开(公告)日：2012-02-28
申请号：US12620045
申请日：2009-11-17
申请人： Hiroshi Ohta , Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
发明人： Hiroshi Ohta , Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/7395 , H01L29/7811 , Y10S257/901
摘要： In a vertical power semiconductor device having the super junction structure both in a device section and a terminal section, an n-type impurity layer is formed on the outer peripheral surface in the super junction structure. This allows an electric field on the outer peripheral surface of the super junction structure region to be reduced. Accordingly, a reliable vertical power semiconductor device of a high withstand voltage can be provided.
摘要翻译：在器件部分和端子部分都具有超结结构的垂直功率半导体器件中，在超结结构的外周表面上形成n型杂质层。这允许减小超结结构区域的外周表面上的电场。因此，可以提供高耐受电压的可靠的垂直功率半导体器件。

34. 发明申请

US20100123186A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20100123186A1
公开(公告)日：2010-05-20
申请号：US12620045
申请日：2009-11-17
申请人： Hiroshi Ohta , Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
发明人： Hiroshi Ohta , Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/7395 , H01L29/7811 , Y10S257/901
摘要： In a vertical power semiconductor device having the super junction structure both in a device section and a terminal section, an n-type impurity layer is formed on the outer peripheral surface in the super junction structure. This allows an electric field on the outer peripheral surface of the super junction structure region to be reduced. Accordingly, a reliable vertical power semiconductor device of a high withstand voltage can be provided.
摘要翻译：在器件部分和端子部分都具有超结结构的垂直功率半导体器件中，在超结结构的外周表面上形成n型杂质层。这允许减小超结结构区域的外周表面上的电场。因此，可以提供高耐受电压的可靠的垂直功率半导体器件。

35. 发明授权

US07755138B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07755138B2
公开(公告)日：2010-07-13
申请号：US12537219
申请日：2009-08-06
申请人： Wataru Saito , Syotaro Ono , Nana Hatano , Hiroshi Ohta , Miho Watanabe
发明人： Wataru Saito , Syotaro Ono , Nana Hatano , Hiroshi Ohta , Miho Watanabe
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/7806
摘要： A semiconductor device of the invention includes: a super junction structure of an n-type pillar layer and a p-type pillar layer; a base layer provided on the p-type pillar layer; a source layer selectively provided on a surface of the base layer; a gate insulating film provided on a portion being in contact with the base layer, a portion being in contact with the source layer and a portion being in contact with the n-type pillar layer on a portion of a junction between the n-type pillar layer and the p-type pillar layer; a control electrode provided opposed to the base layer, the source layer and the n-type pillar layer through the gate insulating film; and a source electrode electrically connected to the base layer, the source layer and the n-type layer. The source electrode is contact with the surface of the n-type pillar layer located between the control electrodes to form a Schottky junction.
摘要翻译：本发明的半导体器件包括：n型柱层和p型柱层的超结结构; 设置在p型支柱层上的基底层; 源层选择性地设置在基层的表面上; 设置在与所述基底层接触的部分上的栅极绝缘膜，与所述源极层接触的部分和在所述n型支柱的接合部的一部分上与所述n型支柱层接触的部分层和p型支柱层; 控制电极，其通过所述栅极绝缘膜与所述基极层，所述源极层和所述n型支柱层相对设置; 以及与基极层，源极层和n型层电连接的源电极。源电极与位于控制电极之间的n型支柱层的表面接触以形成肖特基结。

36. 发明授权

US08643056B2 Power semiconductor device and method of manufacturing the same 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US08643056B2
公开(公告)日：2014-02-04
申请号：US13229203
申请日：2011-09-09
申请人： Kiyoshi Kimura , Yasuto Sumi , Hiroshi Ohta , Hiroyuki Irifune
发明人： Kiyoshi Kimura , Yasuto Sumi , Hiroshi Ohta , Hiroyuki Irifune
IPC分类号： H01L29/66
CPC分类号： H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/7811 , H01L29/872
摘要： A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers. The plurality of third second-conductivity-type pillar layers are arranged on the first epitaxial layer.
摘要翻译：功率半导体器件包括第一导电类型的第一半导体层，第一漂移层和第二漂移层。第一漂移层包括第一导电类型的第一外延层，多个第一第一导电型柱层和多个第一第二导电型柱层。第二漂移层形成在第一漂移层上，并且包括第一导电类型的第二外延层，多个第二第二导电型柱层，多个第二第一导电型柱层，多个第二导电型柱层第三第二导电型柱层和多个第三第一导电型柱层。多个第二第二导电型柱层与第一第二导电型柱层连接。多个第二第一导电型柱层与第一第一导电型柱层连接。多个第三第二导电型柱层布置在第一外延层上。

37. 发明申请

US20110291181A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110291181A1
公开(公告)日：2011-12-01
申请号：US13149345
申请日：2011-05-31
申请人： Hiroyuki IRIFUNE , Yasuto Sumi , Kiyoshi Kimura , Hiroshi Ohta
发明人： Hiroyuki IRIFUNE , Yasuto Sumi , Kiyoshi Kimura , Hiroshi Ohta
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66712 , H01L29/0626 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/404 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： According to one embodiment, a semiconductor device including a cell region and a terminal region includes a first semiconductor region of a first conductivity type, semiconductor pillars of the first and a second conductivity type, a second semiconductor region of the second conductivity type, and a third semiconductor region of the first conductivity type. The semiconductor pillars of the first and second conductivity type are and arranged alternately on the first semiconductor region. The second semiconductor region is provided on the semiconductor pillar of the second conductivity type. The third semiconductor region is provided on the second semiconductor region. A semiconductor pillar other than a semiconductor pillar most proximal to the terminal region is provided in a stripe configuration. The semiconductor pillar most proximal to the terminal region includes regions having a high and a low impurity concentration. The regions are provided alternately.
摘要翻译：根据一个实施例，包括单元区域和端子区域的半导体器件包括第一导电类型的第一半导体区域，第一和第二导电类型的半导体柱，第二导电类型的第二半导体区域和第一导电类型的第三半导体区域。第一和第二导电类型的半导体柱交替地布置在第一半导体区域上。第二半导体区域设置在第二导电类型的半导体柱上。第三半导体区域设置在第二半导体区域上。最靠近端子区域的半导体柱以外的半导体柱设置成条状。最靠近末端区域的半导体柱包括具有高和低杂质浓度的区域。这些区域交替地设置。

38. 发明授权

US08680606B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08680606B2
公开(公告)日：2014-03-25
申请号：US13424344
申请日：2012-03-19
申请人： Hiroshi Ohta , Yasuto Sumi , Kiyoshi Kimura , Junji Suzuki , Hiroyuki Irifune
发明人： Hiroshi Ohta , Yasuto Sumi , Kiyoshi Kimura , Junji Suzuki , Hiroyuki Irifune
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/4238 , H01L29/66712
摘要： A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer provided thereon, mutually separated columnar third semiconductor layers of a second conductivity type extending within the second semiconductor layer, island-like fourth semiconductor layers of the second conductivity type provided on the third semiconductor layers, fifth semiconductor layers of the first conductivity type, sixth semiconductor layers of the second conductivity type, a gate electrode, a first electrode, and a second electrode. The fifth semiconductor layers are selectively provided on the fourth semiconductor layers. The sixth semiconductor layer electrically connects two adjacent fourth semiconductor layers. The first electrode is in electrical connection with the first semiconductor. The second electrode is in electrical connection with the fourth semiconductor layers and the fifth semiconductor layers via the openings in the gate electrode.
摘要翻译：功率半导体器件包括第一导电类型的第一半导体层，设置在其上的第二半导体层，在第二半导体层内延伸的第二导电类型的相互分离的柱状第三半导体层，第二导电类型的岛状第四半导体层提供在第三半导体层上的第一半导体层，第一导电类型的第五半导体层，第二导电类型的第六半导体层，栅电极，第一电极和第二电极。第五半导体层选择性地设置在第四半导体层上。第六半导体层电连接两个相邻的第四半导体层。第一电极与第一半导体电连接。第二电极经由栅电极中的开口与第四半导体层和第五半导体层电连接。

39. 发明授权

US09312521B2 Cell, assembled battery, and battery-mounted device 有权
标题翻译：电池，组装电池和电池安装装置
公开(公告)号：US09312521B2
公开(公告)日：2016-04-12
申请号：US14241808
申请日：2011-08-29
申请人： Hiroshi Ohta
发明人： Hiroshi Ohta
IPC分类号： H01M2/06 , H01M2/30 , H01M2/02 , H01M2/22 , H01M2/24 , H01M2/26
CPC分类号： H01M2/06 , H01M2/02 , H01M2/022 , H01M2/024 , H01M2/22 , H01M2/24 , H01M2/26 , H01M2/30 , H01M2/305
摘要： Disclosed is a cell including: a closed-end tubular case for accommodating a power generation element; a lid for the case; a terminal electrode disposed outside of the case and used for connection with another cell; an extraction electrode passing through the lid and used to extract power of the power generation element to the outside of the case; and a stepped connection electrode disposed outside of the case, the stepped connection electrode having a first flat portion to which the terminal electrode is connected and a second flat portion which is located at a level different from the level of the first flat portion and to which the extraction electrode is connected. The first and second flat portions have regions overlapping each other as viewed in a direction orthogonal to the thickness of the first and second flat portions.
摘要翻译：公开了一种电池，包括：用于容纳发电元件的封闭端管状壳体; 一箱盖; 端子电极，设置在壳体的外部并用于与另一个电池连接; 通过所述盖并用于将所述发电元件的功率提取到所述壳体的外部的引出电极; 以及设置在所述壳体的外侧的阶梯状连接电极，所述阶梯状连接电极具有与所述端子电极连接的第一平坦部，以及位于与所述第一平坦部的高度不同的水平面的第二平坦部，引出电极连接。当与第一和第二平坦部分的厚度正交的方向观察时，第一和第二平坦部分具有彼此重叠的区域。

40. 发明授权

US08623898B2 Glycine transporter inhibiting substances 失效
标题翻译：甘氨酸转运蛋白抑制物质
公开(公告)号：US08623898B2
公开(公告)日：2014-01-07
申请号：US13257258
申请日：2010-03-19
申请人： Akito Yasuhara , Shuji Yamamoto , Hiroshi Ohta , Yoshihisa Shirasaki , Kazunari Sakagami , Masato Hayashi , Tsuyoshi Shibata , Youichi Shimazaki , Yuko Araki , Kumi Abe , Xiang-Min Sun
发明人： Akito Yasuhara , Shuji Yamamoto , Hiroshi Ohta , Yoshihisa Shirasaki , Kazunari Sakagami , Masato Hayashi , Tsuyoshi Shibata , Youichi Shimazaki , Yuko Araki , Kumi Abe , Xiang-Min Sun
IPC分类号： C07D471/04 , C07D405/12 , C07D409/12 , C07D405/14 , A01N43/64 , A01N43/50 , A61K31/41
CPC分类号： C07D471/04 , C07D405/12 , C07D405/14 , C07D409/12
摘要： The present invention aims to provide novel compounds of formula [I] or pharmaceutically acceptable salts thereof that are based on a glycine uptake inhibiting action and which are useful in the prevention or treatment of such diseases as schizophrenia, Alzheimer's disease, cognitive dysfunction, dementia, anxiety disorders (generalized anxiety disorder, panic disorder, obsessive-compulsory disorder, social anxiety disorder, posttraumatic stress disorder, specific phobia, acute stress disorder, etc.), depression, drug addiction, spasm, tremor, and sleep disorder:
摘要翻译：本发明旨在提供基于甘氨酸摄取抑制作用的新颖的式[I]化合物或其药学上可接受的盐，其可用于预防或治疗精神分裂症，阿尔茨海默病，认知功能障碍，痴呆，焦虑症（广泛性焦虑障碍，恐慌症，强迫症，社会焦虑症，创伤后应激障碍，特定恐惧症，急性应激障碍等），抑郁症，药物成瘾，痉挛，震颤和睡眠障碍：

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