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31. 发明授权

US06858492B2 Method for fabricating a semiconductor memory device 失效
标题翻译：半导体存储器件的制造方法
公开(公告)号：US06858492B2
公开(公告)日：2005-02-22
申请号：US10186597
申请日：2002-07-01
申请人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
发明人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L21/8242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/91
摘要： Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration extending into the third dimension. A contacting of plug regions is performed after producing the capacitor devices. Such capacitor devices provide an increased integration density in a semiconductor memory device.
摘要翻译：电容器器件以基本上垂直延伸的方式形成，以便实现基本上三维配置或延伸到第三维度的配置。在制造电容器装置之后，进行插塞区域的接触。这种电容器器件在半导体存储器件中提供增加的集成密度。

32. 发明授权

US06818503B2 Method for fabricating a semiconductor memory device 失效
标题翻译：半导体存储器件的制造方法
公开(公告)号：US06818503B2
公开(公告)日：2004-11-16
申请号：US10186607
申请日：2002-07-01
申请人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Igor Kasko , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner , Volker Weinrich
发明人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Igor Kasko , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner , Volker Weinrich
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L28/60
摘要： A method of fabricating semiconductor memory devices is simplified by providing at least some plug regions, which are provided for contacting storage capacitor devices of a capacitor configuration, such that the plug regions have in each case a region that is elevated above the surface region of a passivation region.
摘要翻译：通过提供至少一些插塞区域来简化制造半导体存储器件的方法，这些插塞区域被提供用于接触电容器配置的存储电容器器件，使得插塞区域在每种情况下都具有在钝化区。

33. 发明授权

US06649483B2 Method for fabricating a capacitor configuration 有权
公开(公告)号：US06649483B2
公开(公告)日：2003-11-18
申请号：US09996959
申请日：2001-11-20
申请人： Walter Hartner , Volker Weinrich , Matthias Krönke
发明人： Walter Hartner , Volker Weinrich , Matthias Krönke
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L21/76895 , H01L28/60 , H01L28/90
摘要： A method for fabricating a capacitor configuration in particular an FeRAM memory device includes the step of filling intermediate regions, which remain free after the formation of a capacitor device on a surface of a substrate, with at least one electrically insulating intermediate layer. The at least one electrically insulating intermediate layer is filled at least up to a level of a topmost layer of the capacitor device.

34. 发明授权

US07982284B2 Semiconductor component including an isolation structure and a contact to the substrate 有权
标题翻译：半导体元件包括隔离结构和与衬底的接触
公开(公告)号：US07982284B2
公开(公告)日：2011-07-19
申请号：US11477076
申请日：2006-06-28
申请人： Andreas Meiser , Walter Hartner , Hermann Gruber , Dietrich Bonart , Thomas Gross
发明人： Andreas Meiser , Walter Hartner , Hermann Gruber , Dietrich Bonart , Thomas Gross
IPC分类号： H01L21/763 , H01L27/105
CPC分类号： H01L21/76802 , H01L21/76286 , H01L21/76877 , H01L21/84 , H01L27/1203
摘要： A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.
摘要翻译：半导体部件包括半导体本体，其中形成有：第一导电类型的衬底，布置在衬底上的第二导电类型的埋入半导体层，以及布置在埋置的第三导电类型的功能单元半导体层半导体层，其中设置有横向彼此排列的至少两个半导体功能单元。掩埋半导体层是至少一个半导体功能单元的一部分，半导体功能单元通过渗透功能单元半导体层，埋入半导体层和基板的隔离结构彼此电绝缘。隔离结构包括至少一个沟槽和与衬底的导电接触，与衬底的接触通过至少一个沟槽与功能单元半导体层和掩埋层电绝缘。

35. 发明申请

US20080012090A1 Semiconductor component and methods for producing a semiconductor component 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US20080012090A1
公开(公告)日：2008-01-17
申请号：US11477076
申请日：2006-06-28
申请人： Andreas Meiser , Walter Hartner , Hermann Gruber , Dietrich Bonart , Thomas Gross
发明人： Andreas Meiser , Walter Hartner , Hermann Gruber , Dietrich Bonart , Thomas Gross
IPC分类号： H01L29/00
CPC分类号： H01L21/76802 , H01L21/76286 , H01L21/76877 , H01L21/84 , H01L27/1203
摘要： A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.
摘要翻译：半导体部件包括半导体本体，其中形成有：第一导电类型的衬底，布置在衬底上的第二导电类型的埋入半导体层，以及布置在埋置的第三导电类型的功能单元半导体层半导体层，其中设置有横向彼此排列的至少两个半导体功能单元。掩埋半导体层是至少一个半导体功能单元的一部分，半导体功能单元通过渗透功能单元半导体层，埋入半导体层和基板的隔离结构彼此电绝缘。隔离结构包括至少一个沟槽和与衬底的导电接触，与衬底的接触通过至少一个沟槽与功能单元半导体层和掩埋层电绝缘。

36. 发明授权

US07078309B2 Methods for producing a structured metal layer 失效
公开(公告)号：US07078309B2
公开(公告)日：2006-07-18
申请号：US09734467
申请日：2000-12-11
申请人： Gerhard Beitel , Annette Sänger , Walter Hartner
发明人： Gerhard Beitel , Annette Sänger , Walter Hartner
IPC分类号： H01L21/20
CPC分类号： C23C16/409 , H01L21/3212 , H01L28/55 , H01L28/60 , H01L28/75
摘要： The invention provides methods which can be used to structure even precious metal electrodes with conventional CMP steps, in particular with the aid of conventional slurries such as are already used to structure non-precious metals. Owing to the formation of an alloy, the chemically active components of the slurry are capable of attacking the additive to the precious metal in the alloy, as a result of which the surface of the alloy layer is roughened and the mechanical removal of the precious metal is increased.

37. 发明授权

US06809019B2 Method for producing a semiconductor structure, and use of the method 失效
标题翻译：半导体结构的制造方法以及使用该方法
公开(公告)号：US06809019B2
公开(公告)日：2004-10-26
申请号：US10261849
申请日：2002-09-30
申请人： Walter Hartner , Matthias Krönke
发明人： Walter Hartner , Matthias Krönke
IPC分类号： H01L213205
CPC分类号： H01L28/91
摘要： A method for producing a semiconductor structure includes applying at least one first layer, etching the first layer using a masking layer such that fences are produced, and, after removal of the masking layer and application of an auxiliary layer, the auxiliary layer and the fences are removed jointly except for a predetermined extent of the auxiliary layer. The present invention also relates to use of the method for producing spacers in a semiconductor structure.
摘要翻译：一种制造半导体结构的方法包括：施加至少一个第一层，使用掩模层蚀刻第一层以产生栅栏，并且在去除掩模层和施加辅助层之后，辅助层和栅栏除了辅助层的预定范围外联合除去。本发明还涉及在半导体结构中制造间隔物的方法的用途。

38. 发明授权

US06773986B2 Method for fabricating a semiconductor memory device 失效
标题翻译：半导体存储器件的制造方法
公开(公告)号：US06773986B2
公开(公告)日：2004-08-10
申请号：US10186662
申请日：2002-07-01
申请人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
发明人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： To achieve a highest possible integration density in a semiconductor memory device having storage capacitors as storage elements, the method according to the invention forms the capacitor devices in substantially vertically extending fashion, to, as a result, achieve a substantially three-dimensional configuration and an configuration extending into the third dimension for the capacitor devices, a contact connection of the storage capacitors being formed after the production of the storage capacitors.
摘要翻译：为了在具有存储电容器作为存储元件的半导体存储器件中实现最高可能的积分密度，根据本发明的方法以基本上垂直延伸的方式形成电容器器件，结果实现基本上三维配置和配置延伸到用于电容器器件的第三维度中，在存储电容器的生产之后形成存储电容器的接触连接。

39. 发明授权

US06704219B2 FeRAM memory and method for manufacturing it 失效
标题翻译： FeRAM存储器及其制造方法
公开(公告)号：US06704219B2
公开(公告)日：2004-03-09
申请号：US10186645
申请日：2002-07-01
申请人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
发明人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , H01L28/86
摘要： To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices used as storage elements with a multiplicity of individual capacitors that are connected in parallel with one another. The individual capacitors have ferroelectric or paraelectric dielectric regions with different coercitive voltages such that there is a resulting multiplicity of storage states for each of the individual capacitors.
摘要翻译：为了以特别节省空间的方式制造FeRAM存储器，因此增加存储密度，制造方法形成用作存储元件的多个电容器器件中的至少一些，其中多个单独的电容器与一个并联连接另一个。各个电容器具有不同强制电压的铁电或对称电介质区域，使得每个单独的电容器存在多个存储状态。

40. 发明授权

US06171934B2 Recovery of electronic properties in process-damaged ferroelectrics by voltage-cycling 失效
标题翻译：通过电压循环恢复工艺损坏的铁电体中的电子特性
公开(公告)号：US06171934B2
公开(公告)日：2001-01-09
申请号：US09144297
申请日：1998-08-31
申请人： Vikram Joshi , Narayan Solayappan , Walter Hartner , G{umlaut over (u)}nther Schindler
发明人： Vikram Joshi , Narayan Solayappan , Walter Hartner , G{umlaut over (u)}nther Schindler
IPC分类号： H01L21326
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： An integrated circuit is formed containing a metal-oxide ferroelectric thin film. An voltage-cycling recovery process is conducted to reverse the degradation of ferroelectric properties caused by hydrogen. The voltage-cycling recovery process is conducted by applying from 104 to 1011 voltage cycles with a voltage amplitude of from 1 to 15 volts. Conducting voltage-cycling at a higher temperature in the range 30-200° C. enhances recovery. Preferably the metal oxide thin film comprises layered superlattice material. Preferably the layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate. If the integrated circuit manufacture includes a forming-gas anneal, then the voltage-cycling recovery process is performed after the forming-gas anneal. The voltage-cycling recovery process obviates oxygen-recovery annealing, and it allows continued use of conventional hydrogen-rich plasma processes and forming-gas anneals without the risk of permanent damage to the ferroelectric thin film.
摘要翻译：形成含有金属氧化物铁电体薄膜的集成电路。进行电压循环恢复处理以逆转由氢引起的铁电性能的降低。通过施加电压幅度为1至15伏特的104至1011个电压周期来执行电压循环恢复过程。在30-200℃范围内的较高温度下进行电压循环，提高了回收率。优选地，金属氧化物薄膜包括层状超晶格材料。优选地，层状超晶格材料包括钽酸铋钽铋或铌酸铋钽酸铋。如果集成电路制造包括成形气体退火，则在成形气体退火之后执行电压循环恢复过程。电压循环恢复过程避免氧回收退火，并且其允许继续使用常规富氢等离子体工艺和形成气体退火，而不会对铁电薄膜造成永久损坏的风险。

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