专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07511717B1 Antialiasing using hybrid supersampling-multisampling 有权
标题翻译：使用混合超采样多采样的抗混叠
公开(公告)号：US07511717B1
公开(公告)日：2009-03-31
申请号：US11182676
申请日：2005-07-15
申请人： Rui M. Bastos , Steven E. Molnar , Michael J. M. Toksvig , Matthew J. Craighead
发明人： Rui M. Bastos , Steven E. Molnar , Michael J. M. Toksvig , Matthew J. Craighead
IPC分类号： G09G5/00 , G09G5/02
CPC分类号： G09G3/2074 , G06T11/40 , G09G5/363 , G09G2320/02 , G09G2340/0414 , G09G2340/0421 , G09G2360/18
摘要： Hybrid sampling of pixels of an image involves generating shading values at multiple shading sample locations and generating depth values at multiple depth sample locations, with the number of depth sample locations exceeding the number of shading sample locations. Each shading sample location is associated with one or more of the depth sample locations. Generation and filtering of hybrid sampled pixel data can be done within a graphics processing system, transparent to an application that provides image data.
摘要翻译：图像的像素的混合采样涉及在多个阴影采样位置处生成阴影值，并在多个深度采样位置生成深度值，深度采样位置的数量超过阴影采样位置的数量。每个阴影样本位置与一个或多个深度样本位置相关联。混合采样像素数据的生成和滤波可以在对提供图像数据的应用程序透明的图形处理系统内完成。

32. 发明授权

US06975321B1 System and method for generating multiple outputs in a single shader processing pass in a hardware graphics pipeline 有权
标题翻译：用于在硬件图形管道中的单个着色器处理通过中生成多个输出的系统和方法
公开(公告)号：US06975321B1
公开(公告)日：2005-12-13
申请号：US10430629
申请日：2003-05-05
申请人： John Erik Lindholm , Steven E. Molnar , Harold Robert Feldman Zatz
发明人： John Erik Lindholm , Steven E. Molnar , Harold Robert Feldman Zatz
IPC分类号： G06T15/00 , G06T15/80
CPC分类号： G06T15/005
摘要： A system and method are provided for generating multiple output packets in a single processing pass of a shader in a hardware graphics pipeline. Initially, graphics data is received, after which it is processed utilizing the shader of the hardware graphics pipeline to generate a plurality of output packets. The plurality of output packets is outputted from the shader of the hardware graphics pipeline in the single processing pass.
摘要翻译：提供了一种用于在硬件图形管线中的着色器的单个处理通过中生成多个输出分组的系统和方法。最初，接收图形数据，然后利用硬件图形流水线的着色器对其进行处理，以产生多个输出分组。多个输出分组在单个处理过程中从硬件图形流水线的着色器输出。

33. 发明授权

US5481669A Architecture and apparatus for image generation utilizing enhanced memory devices 失效
标题翻译：利用增强型存储器件进行图像生成的架构和装置
公开(公告)号：US5481669A
公开(公告)日：1996-01-02
申请号：US383969
申请日：1995-02-06
申请人： John W. Poulton , Steven E. Molnar , John G. Eyles
发明人： John W. Poulton , Steven E. Molnar , John G. Eyles
IPC分类号： G09G5/36 , G06T11/00 , G06T11/20 , G06T15/00 , G09G5/393 , G06F12/00
CPC分类号： G09G5/393 , G06T15/005
摘要： A system for image generation comprising a plurality of renderers, each having a geometry processor and a rasterizer, that operate in parallel to compute pixel values for a set of primitive objects that comprise the image to be rendered. The geometry processor transforms graphics primitive objects from their native object coordinates to screen coordinates. The rasterizer consists of an array of enhanced memory devices having a processor and memory for each pixel in a region of a screen. The processors and their associated memories operate in SIMD fashion on screen space primitive descriptions to compute and store pixel values for an entire such region. The enhanced memory devices further comprise compositors for combining their pixel values, for example, based on a visibility test, with those from a corresponding memory device of another rasterizer. The image generation system may further comprise shaders, which compute pixel colors based on pixel values computed in the plurality of renderers, and video frame buffers, which store these pixel colors and refresh a raster display device. The shaders and frame buffers consist of a renderer with additional memory devices that store texture and image data. Also disclosed are enhanced memory devices and rasterizers for use in the present image generation system.
摘要翻译：一种用于图像生成的系统，包括多个渲染器，每个渲染器具有并行操作的几何处理器和光栅化器，以计算一组包含要渲染的图像的原始对象的像素值。几何处理器将图形原始对象从其本机对象坐标转换为屏幕坐标。光栅化器由对屏幕区域中的每个像素具有处理器和存储器的增强型存储器件阵列组成。处理器及其相关存储器以SIMD方式在屏幕空间原始描述上操作以计算和存储整个这样的区域的像素值。增强的存储器件还包括用于将其像素值（例如，基于可见性测试）与来自另一光栅器的相应存储器件的像素值组合的合成器。图像生成系统还可以包括着色器，其基于在多个渲染器中计算的像素值来计算像素颜色，以及存储这些像素颜色并刷新光栅显示装置的视频帧缓冲器。着色器和帧缓冲器由具有存储纹理和图像数据的附加存储器件的渲染器组成。还公开了用于当前图像生成系统的增强型存储器件和光栅化器。

34. 发明授权

US5388206A Architecture and apparatus for image generation 失效
标题翻译：用于图像生成的架构和设备
公开(公告)号：US5388206A
公开(公告)日：1995-02-07
申请号：US975821
申请日：1992-11-13
申请人： John W. Poulton , Steven E. Molnar , John G. Eyles
发明人： John W. Poulton , Steven E. Molnar , John G. Eyles
IPC分类号： G09G5/36 , G06T11/00 , G06T11/20 , G06T15/00 , G09G5/393 , G06F3/14
CPC分类号： G09G5/393 , G06T15/005
摘要： A system for image generation comprising a plurality of renderers, each having a geometry processor and a rasterizer, that operate in parallel to compute pixel values for a set of primitive objects that comprise the image to be rendered. The geometry processor transforms graphics primitive objects from their native object coordinates to screen coordinates. The rasterizer consists of an array of enhanced memory devices having a processor and memory for each pixel in a region of a screen. The processors and their associated memories operate in SIMD fashion on screen space primitive descriptions to compute and store pixel values for an entire such region. The enhanced memory devices further comprise compositors for combining their pixel values, for example, based on a visibility test, with those from a corresponding memory device of another rasterizer. The image generation system may further comprise shaders, which compute pixel colors based on pixel values computed in the plurality of renderers, and video frame buffers, which store these pixel colors and refresh a raster display device. The shaders and frame buffers consist of a renderer with additional memory devices that store texture and image data. Also disclosed are enhanced memory devices and rasterizers for use in the present image generation system.
摘要翻译：一种用于图像生成的系统，包括多个渲染器，每个渲染器具有并行操作的几何处理器和光栅化器，以计算一组包含要渲染的图像的原始对象的像素值。几何处理器将图形原始对象从其本机对象坐标转换为屏幕坐标。光栅化器由对屏幕区域中的每个像素具有处理器和存储器的增强型存储器件阵列组成。处理器及其相关存储器以SIMD方式在屏幕空间原始描述上操作以计算和存储整个这样的区域的像素值。增强的存储器件还包括用于将其像素值（例如，基于可见性测试）与来自另一光栅器的相应存储器件的像素值组合的合成器。图像生成系统还可以包括着色器，其基于在多个渲染器中计算的像素值来计算像素颜色，以及存储这些像素颜色并刷新光栅显示装置的视频帧缓冲器。着色器和帧缓冲器由具有存储纹理和图像数据的附加存储器件的渲染器组成。还公开了用于当前图像生成系统的增强型存储器件和光栅化器。

35. 发明授权

US08627041B2 Efficient line and page organization for compression status bit caching 有权
标题翻译：用于压缩状态位缓存的高效线和页组织
公开(公告)号：US08627041B2
公开(公告)日：2014-01-07
申请号：US12901452
申请日：2010-10-08
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts , Cass W. Everitt , Steven E. Molnar
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts , Cass W. Everitt , Steven E. Molnar
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/08 , G06F12/0875 , G06F12/1009 , G06F2212/401
摘要： One embodiment of the present invention sets forth a technique for performing a memory access request to compressed data within a virtually mapped memory system comprising an arbitrary number of partitions. A virtual address is mapped to a linear physical address, specified by a page table entry (PTE). The PTE is configured to store compression attributes, which are used to locate compression status for a corresponding physical memory page within a compression status bit cache. The compression status bit cache operates in conjunction with a compression status bit backing store. If compression status is available from the compression status bit cache, then the memory access request proceeds using the compression status. If the compression status bit cache misses, then the miss triggers a fill operation from the backing store. After the fill completes, memory access proceeds using the newly filled compression status information.
摘要翻译：本发明的一个实施例提出了一种对包括任意数量的分区的虚拟映射的存储器系统中的压缩数据执行存储器访问请求的技术。虚拟地址被映射到由页表项（PTE）指定的线性物理地址。 PTE被配置为存储压缩属性，其用于定位压缩状态位缓存内的对应物理存储器页的压缩状态。压缩状态位缓存与压缩状态位后备存储一起操作。如果从压缩状态位缓存获得压缩状态，则存储器访问请求使用压缩状态进行。如果压缩状态位缓存未命中，则错误触发后备存储器的填充操作。填充完成后，使用新填充的压缩状态信息进行内存访问。

36. 发明授权

US08605087B2 Hybrid multisample/supersample antialiasing 有权
公开(公告)号：US08605087B2
公开(公告)日：2013-12-10
申请号：US12167998
申请日：2008-07-03
申请人： Cass W. Everitt , Steven E. Molnar
发明人： Cass W. Everitt , Steven E. Molnar
IPC分类号： G06T15/50
CPC分类号： G06T15/503 , G06T11/40 , G06T2200/28 , G06T2210/52
摘要： A system and method for dynamically adjusting the pixel sampling rate during primitive shading can improve image quality or increase shading performance. Hybrid antialiasing is performed by selecting a number of shaded samples per pixel fragment. A combination of supersample and multisample antialiasing is used where a cluster of sub-pixel samples (multisamples) is processed for each pass through a fragment shader pipeline. The number of shader passes and multisamples in each cluster can be determined dynamically for each primitive based on rendering state.

37. 发明授权

US08605086B2 Hybrid multisample/supersample antialiasing 有权
标题翻译：混合多采样/超采样抗锯齿
公开(公告)号：US08605086B2
公开(公告)日：2013-12-10
申请号：US12167997
申请日：2008-07-03
申请人： Cass W. Everitt , Steven E. Molnar
发明人： Cass W. Everitt , Steven E. Molnar
IPC分类号： G06T15/50
CPC分类号： G06T11/40
摘要： A system and method for dynamically adjusting the pixel sampling rate during primitive shading can improve image quality or increase shading performance. Hybrid antialiasing is performed by selecting a number of shaded samples per pixel fragment. A combination of supersample and multisample antialiasing is used where a cluster of sub-pixel samples (multisamples) is processed for each pass through a fragment shader pipeline. The number of shader passes and multisamples in each cluster can be determined dynamically for each primitive based on rendering state.
摘要翻译：在原始着色中动态调整像素采样率的系统和方法可以提高图像质量或增加遮蔽性能。通过选择每个像素片段的阴影样本数来执行混合抗混叠。使用超采样和多采样抗锯齿的组合，其中对于通过片段着色器管线的每次通过处理子像素采样（多采样）的簇。可以基于呈现状态为每个基元动态地确定每个集群中的着色器遍数和多个样本的数量。

38. 发明授权

US08228338B1 Hardware override of application programming interface programmed state 有权
标题翻译：硬件覆盖应用程序编程接口编程状态
公开(公告)号：US08228338B1
公开(公告)日：2012-07-24
申请号：US11625136
申请日：2007-01-19
申请人： Jerome F. Duluk, Jr. , Henry P. Moreton , Steven E. Molnar , John S. Montrym
发明人： Jerome F. Duluk, Jr. , Henry P. Moreton , Steven E. Molnar , John S. Montrym
IPC分类号： G06F13/14 , G06F11/00 , G06T1/00
CPC分类号： G06F11/0793 , G06F11/0715 , G06F11/0751
摘要： A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.
摘要翻译：使用应用编程接口（API）将编程到处理器中的状态信息进行覆盖的方法和系统避免了在处理器中引入错误状况。处理器内的覆盖监视单元存储被覆盖的任何设置的编程状态，以便当错误条件不再存在时可以恢复编程状态。覆盖监视器单元通过强制设置为不引起错误条件的合法值来覆盖编程状态。处理器能够在不通知设备驱动程序的情况下继续运行，因为避免了错误条件，所以发生了错误状况。

39. 发明授权

US08085272B1 Method and system for improving data coherency in a parallel rendering system 有权
标题翻译：用于提高并行渲染系统中数据一致性的方法和系统
公开(公告)号：US08085272B1
公开(公告)日：2011-12-27
申请号：US11556657
申请日：2006-11-03
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
IPC分类号： G06F15/80
CPC分类号： G06T15/005
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a common input stream, tracking a periodic event associated with the common input stream, generating a plurality of fragment streams from the common input stream, inserting a marker based on an occurrence of the periodic event in a first fragment stream in the multiple fragment streams, and utilizing the marker to influence the processing of the first fragment stream so that a plurality of raster operation (ROP) request streams maintains substantially the same coherence as the common input stream. Each fragment stream is independently processed and corresponds to one of the ROP request streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种方法，其包括以下步骤：接收公共输入流，跟踪与公共输入流相关联的周期性事件，从公共输入流生成多个片段流，插入标记基于所述多个片段流中的第一片段流中的所述周期性事件的发生，并且利用所述标记来影响所述第一片段流的处理，使得多个光栅操作（ROP）请求流保持基本相同的一致性公共输入流。每个片段流被独立地处理并对应于其中一个ROP请求流。

40. 发明授权

US07999820B1 Methods and systems for reusing memory addresses in a graphics system 有权
标题翻译：在图形系统中重复使用存储器地址的方法和系统
公开(公告)号：US07999820B1
公开(公告)日：2011-08-16
申请号：US11953812
申请日：2007-12-10
申请人： Adam Clark Weitkemper , Steven E. Molnar , Mark J. French , Cass W. Everitt
发明人： Adam Clark Weitkemper , Steven E. Molnar , Mark J. French , Cass W. Everitt
IPC分类号： G06F12/02 , G06F12/10 , G06F12/06
CPC分类号： G06F12/0223 , G06F12/10 , G09G5/39 , G09G2360/122
摘要： Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint on a display screen to a group of contiguous physical memory locations in a memory system, determining an anchor physical memory address from a first transaction associated with the footprint, wherein the anchor physical memory address corresponds to an anchor in the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits (LSBs) associated with the second transaction, and combining the anchor physical memory address with the set of LSBs associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.
摘要翻译：公开了用于重新使用图形系统中的存储器地址的方法和系统，从而可以减少地址转换硬件的实例。本发明的一个实施例提出了一种方法，其包括将显示屏幕上的占位面积映射到存储器系统中的一组连续物理存储器位置，从与所述覆盖区相关联的第一事务确定锚物理存储器地址，其中，锚物理存储器地址对应于连续物理存储器位置组中的锚点，确定也与占用空间相关联的第二事务，确定与第二事务相关联的一组最低有效位（LSB），以及组合锚物理存储器地址与与第二事务相关联的一组LSB产生用于第二事务的第二物理存储器地址，从而避免第二次完全地址转换。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式