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31. 发明授权

US08330208B2 Ultrahigh density monolithic three dimensional vertical NAND string memory device and method of making thereof 有权
标题翻译：超高密度单片三维垂直NAND串存储器件及其制造方法
公开(公告)号：US08330208B2
公开(公告)日：2012-12-11
申请号：US13451009
申请日：2012-04-19
申请人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
发明人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
IPC分类号： H01L29/788
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.
摘要翻译：单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

32. 发明申请

US20110309430A1 Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation 有权
标题翻译：具有扁平单元结构和空气间隙隔离的非易失性存储器
公开(公告)号：US20110309430A1
公开(公告)日：2011-12-22
申请号：US13162550
申请日：2011-06-16
申请人： Vinod Robert Purayath , George Matamis , Henry Chien , James Kai , Yuan Zhang
发明人： Vinod Robert Purayath , George Matamis , Henry Chien , James Kai , Yuan Zhang
IPC分类号： H01L29/788 , H01L21/764
CPC分类号： H01L27/11524 , H01L21/28273 , H01L21/28282 , H01L21/764 , H01L21/7682 , H01L27/11521 , H01L27/11568 , H01L29/0649
摘要： High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.
摘要翻译：高密度半导体存储器提供了非易失性存储器中分立器件之间的栅极耦合和电隔离的增强。控制栅极和电荷存储区域之间的中间电介质在行方向上变化，不同的介电常数用于不同的材料以提供足够的栅极间耦合，同时防止边缘场和寄生电容。至少部分地通过在列（位线）方向上形成的气隙和/或在行（字线）方向上形成的气隙来进一步提供电隔离。

33. 发明授权

US08946048B2 Method of fabricating non-volatile memory with flat cell structures and air gap isolation 有权
标题翻译：制造具有扁平电池结构和气隙隔离的非易失性存储器的方法
公开(公告)号：US08946048B2
公开(公告)日：2015-02-03
申请号：US13162550
申请日：2011-06-16
申请人： Vinod Robert Purayath , George Matamis , Henry Chien , James Kai , Yuan Zhang
发明人： Vinod Robert Purayath , George Matamis , Henry Chien , James Kai , Yuan Zhang
IPC分类号： H01L21/76
CPC分类号： H01L27/11524 , H01L21/28273 , H01L21/28282 , H01L21/764 , H01L21/7682 , H01L27/11521 , H01L27/11568 , H01L29/0649
摘要： High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.
摘要翻译：高密度半导体存储器提供了非易失性存储器中分立器件之间的栅极耦合和电隔离的增强。控制栅极和电荷存储区域之间的中间电介质在行方向上变化，不同的介电常数用于不同的材料以提供足够的栅极间耦合，同时防止边缘场和寄生电容。至少部分地通过在列（位线）方向上形成的气隙和/或在行（字线）方向上形成的气隙来进一步提供电隔离。

34. 发明授权

US08187936B2 Ultrahigh density vertical NAND memory device and method of making thereof 有权
标题翻译：超高密度垂直NAND存储器件及其制造方法
公开(公告)号：US08187936B2
公开(公告)日：2012-05-29
申请号：US12827947
申请日：2010-06-30
申请人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
发明人： Johann Alsmeier , Vinod Robert Purayath , Henry Chien , George Matamis , Yao-Sheng Lee , James Kai , Yuan Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/788 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： A method of making a monolithic three dimensional NAND string. The method includes forming a stack of alternating layers of a first material and a second material over a substrate. The first material includes a conductive or semiconductor control gate material and the second material includes an insulating material. The method also includes etching the stack to form at least one opening in the stack, selectively etching the first material to form first recesses in the first material and forming a blocking dielectric in the first recesses. The method also includes forming a plurality of discrete charge storage segments separated from each other in the first recesses over the blocking dielectric, forming a tunnel dielectric over a side wall of the discrete charge storage segments exposed in the at least one opening and forming a semiconductor channel in the at least one opening.
摘要翻译：制造单片三维NAND串的方法。该方法包括在衬底上形成第一材料和第二材料的交替层的叠层。第一材料包括导电或半导体控制栅极材料，第二材料包括绝缘材料。该方法还包括蚀刻堆叠以在堆叠中形成至少一个开口，选择性地蚀刻第一材料以在第一材料中形成第一凹槽并在第一凹槽中形成阻挡电介质。该方法还包括在隔离电介质上的第一凹槽中形成彼此分开的多个离散的电荷存储段，在暴露在至少一个开口中的离散电荷存储段的侧壁上形成隧道电介质，并形成半导体通道在至少一个开口中。

35. 发明申请

US20090147576A1 FLOATING GATE WITH UNIVERSAL ETCH STOP LAYER 有权
标题翻译：浮动门与通用灭火层
公开(公告)号：US20090147576A1
公开(公告)日：2009-06-11
申请号：US11951998
申请日：2007-12-06
申请人： George Matamis , Henry Chien , Vinod Robert Purayath , Takashi Whitney Orimoto , James Kai
发明人： George Matamis , Henry Chien , Vinod Robert Purayath , Takashi Whitney Orimoto , James Kai
IPC分类号： G11C16/04 , H01L21/336
CPC分类号： H01L21/28273 , H01L27/10844 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： Floating gates of a floating gate memory array have an inverted-T shape in both the bit line direction and the word line direction. Floating gates are formed using an etch stop layer that separates two polysilicon layers that form floating gates. Word lines extend over floating gates in one example, and word lines extend between floating gates in another example.
摘要翻译：浮动栅极存储器阵列的浮动栅极在位线方向和字线方向都具有倒T形。使用分离形成浮动栅极的两个多晶硅层的蚀刻停止层形成浮动栅极。字线在一个示例中在浮动栅极上延伸，并且在另一示例中，字线在浮动栅极之间延伸。

36. 发明申请

US20080248621A1 Integrated Non-Volatile Memory And Peripheral Circuitry Fabrication 有权
标题翻译：集成非易失性存储器和外围电路制造
公开(公告)号：US20080248621A1
公开(公告)日：2008-10-09
申请号：US12058512
申请日：2008-03-28
申请人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
发明人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
IPC分类号： H01L21/336
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.
摘要翻译：提供非易失性存储器和集成存储器和外围电路制造工艺。使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。中间电介质层设置在电荷存储区域的上方。将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

37. 发明授权

US07582529B2 Methods of fabricating non-volatile memory with integrated peripheral circuitry and pre-isolation memory cell formation 有权
标题翻译：使用集成外围电路和预隔离存储器单元形成制造非易失性存储器的方法
公开(公告)号：US07582529B2
公开(公告)日：2009-09-01
申请号：US12061641
申请日：2008-04-02
申请人： George Matamis , Takashi Orimoto , Masaaki Higashitani , James Kai , Tuan Pham
发明人： George Matamis , Takashi Orimoto , Masaaki Higashitani , James Kai , Tuan Pham
IPC分类号： H01L21/8247
CPC分类号： H01L27/11543 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11541
摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated peripheral circuitry formation are provided. Strips of charge storage material elongated in a row direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. Forming the strips defines the dimension of the resulting charge storage structures in the column direction. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. Strips of control gate material are formed between strips of charge storage material adjacent in the column direction. The strips of charge storage and control gate material are divided along their lengths in the row direction as part of forming isolation trenches and columns of active areas. After dividing the strips, the charge storage material at the peripheral circuitry region of the substrate is etched to define a gate dimension in the column direction for a peripheral transistor. Control gate interconnects can be formed to connect together rows of isolated control gates to extrinsically form word lines.
摘要翻译：提供了具有双控制栅极存储器单元的非易失性半导体存储器件及其使用集成的外围电路形成形成其的方法。形成沿着行方向延伸穿过衬底表面的电荷存储材料带，其间具有隧道介电材料带。形成条带限定了所得电荷存储结构在列方向上的尺寸。在一个实施例中，电荷存储材料条可以包括多层电荷存储材料以形成复合电荷存储结构。控制栅极材料条形成在沿着列方向相邻的电荷存储材料的条带之间。电荷存储和控制栅极材料条沿着它们在行方向上的长度被划分，作为形成隔离沟槽和有源区的列的一部分。在分割条之后，蚀刻衬底的外围电路区域处的电荷存储材料，以便在外围晶体管的列方向上限定栅极尺寸。可以形成控制栅极互连以将行隔离的控制栅极连接在一起，以外部地形成字线。

38. 发明授权

US07592223B2 Methods of fabricating non-volatile memory with integrated select and peripheral circuitry and post-isolation memory cell formation 有权
标题翻译：使用集成选择和外围电路和后隔离存储器单元形成制造非易失性存储器的方法
公开(公告)号：US07592223B2
公开(公告)日：2009-09-22
申请号：US12061642
申请日：2008-04-02
申请人： Tuan Pham , Takashi Orimoto , Masaaki Higashitani , James Kai , George Matamis
发明人： Tuan Pham , Takashi Orimoto , Masaaki Higashitani , James Kai , George Matamis
IPC分类号： H01L21/8247
CPC分类号： H01L27/11543 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11541
摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated select and peripheral circuitry formation are provided. Strips of charge storage material elongated in a column direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. After forming isolation trenches in the substrate between active areas below the strips of charge storage material, spacer-assisted patterning is used to form a pattern at the memory array region. Strips of photoresist are patterned over a portion of the pattern at the memory array. Photoresist is also applied at the peripheral circuitry region. At least a portion of the layer stack is etched using the photoresist as a mask before removing the photoresist and etching the strips of charge storage material to form the charge storage structures.
摘要翻译：提供了具有双控制栅极存储器单元的非易失性半导体存储器件及其使用集成选择和外围电路形成的方法。形成沿着柱方向延伸穿过衬底表面的电荷存储材料带，其间具有隧道介电材料带。在一个实施例中，电荷存储材料条可以包括多层电荷存储材料以形成复合电荷存储结构。在电荷存储材料条带之下的有源区域中的衬底中形成隔离沟槽之后，使用间隔物辅助图案化以在存储器阵列区域形成图案。在存储器阵列上的图案的一部分上图案化的光致抗蚀剂条纹。光刻胶也被应用在外围电路区域。在去除光致抗蚀剂并蚀刻电荷存储材料条之前，使用光致抗蚀剂作为掩模来蚀刻层叠体的至少一部分，以形成电荷存储结构。

39. 发明申请

US20080268596A1 Methods Of Fabricating Non-Volatile Memory With Integrated Select And Peripheral Circuitry And Post-Isolation Memory Cell Formation 有权
标题翻译：使用集成选择和外围电路和后隔离存储器单元形成的非易失性存储器的制造方法
公开(公告)号：US20080268596A1
公开(公告)日：2008-10-30
申请号：US12061642
申请日：2008-04-02
申请人： Tuan Pham , Takashi Orimoto , Masaaki Higashitani , James Kai , George Matamis
发明人： Tuan Pham , Takashi Orimoto , Masaaki Higashitani , James Kai , George Matamis
IPC分类号： H01L21/336
CPC分类号： H01L27/11543 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11541
摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated select and peripheral circuitry formation are provided. Strips of charge storage material elongated in a column direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. After forming isolation trenches in the substrate between active areas below the strips of charge storage material, spacer-assisted patterning is used to form a pattern at the memory array region. Strips of photoresist are patterned over a portion of the pattern at the memory array. Photoresist is also applied at the peripheral circuitry region. At least a portion of the layer stack is etched using the photoresist as a mask before removing the photoresist and etching the strips of charge storage material to form the charge storage structures.
摘要翻译：提供了具有双控制栅极存储器单元的非易失性半导体存储器件及其使用集成选择和外围电路形成的方法。形成沿着柱方向延伸穿过衬底表面的电荷存储材料带，其间具有隧道介电材料带。在一个实施例中，电荷存储材料条可以包括多层电荷存储材料以形成复合电荷存储结构。在电荷存储材料条带之下的有源区域中的衬底中形成隔离沟槽之后，使用间隔物辅助图案化以在存储器阵列区域形成图案。在存储器阵列上的图案的一部分上图案化的光致抗蚀剂条纹。光刻胶也被应用在外围电路区域。在去除光致抗蚀剂并蚀刻电荷存储材料条之前，使用光致抗蚀剂作为掩模来蚀刻层叠体的至少一部分，以形成电荷存储结构。

40. 发明申请

US20080171428A1 Methods of Forming Spacer Patterns Using Assist Layer For High Density Semiconductor Devices 有权
标题翻译：使用高密度半导体器件辅助层形成间隔图的方法
公开(公告)号：US20080171428A1
公开(公告)日：2008-07-17
申请号：US11623314
申请日：2007-01-15
申请人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
发明人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
IPC分类号： H01L21/3205
CPC分类号： H01L21/32139 , H01L21/0337 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译：提供了高密度半导体器件及其制造方法。利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

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