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31. 发明授权

US4994893A Field effect transistor substantially coplanar surface structure 失效
标题翻译：场效应晶体管基本上共面的表面结构
公开(公告)号：US4994893A
公开(公告)日：1991-02-19
申请号：US405284
申请日：1989-09-11
申请人： Hiroji Ozaki , Takahisa Eimori , Yoshinori Tanaka , Wataru Wakamiya , Shinichi Satoh
发明人： Hiroji Ozaki , Takahisa Eimori , Yoshinori Tanaka , Wataru Wakamiya , Shinichi Satoh
IPC分类号： H01L21/3205 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/417
CPC分类号： H01L29/41775 , H01L27/10808
摘要： A semiconductor device has MOS field effect transistors isolated by a field shield. The field shield has a gate of conductor layers formed spaced apart from each other on a silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. In regions isolated by the field shield, MOS field effect transistors are formed. Each of the MOS field effect transistors has a gate electrode of a conductor layer formed on the silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. An impurity diffused region is formed in a region on the silicon substrate between the gate electrode and the field shield. A portion on an exposed surface of the impurity diffused region between the field shield and the gate electrode is selectively filled with a tungsten buried layer. The tungsten buried layer is formed, flattened relative to the gate electrode and the gate constituting the field shield.
摘要翻译：半导体器件具有通过场屏蔽隔离的MOS场效应晶体管。场屏蔽具有通过绝缘膜在硅衬底上彼此隔开形成的导体层的栅极，并且其表面被绝缘膜覆盖。在通过场屏蔽隔离的区域中，形成MOS场效应晶体管。每个MOS场效应晶体管具有通过绝缘膜形成在硅衬底上并且其表面被绝缘膜覆盖的导体层的栅电极。在栅电极和场屏蔽之间的硅衬底上的区域中形成杂质扩散区域。在场屏蔽和栅电极之间的杂质扩散区域的暴露表面上的一部分选择性地填充有钨掩埋层。形成钨掩埋层，相对于构成场屏蔽体的栅电极和栅极变平。

32. 发明授权

US4984055A Semiconductor device having a plurality of conductive layers and manufacturing method therefor 失效
标题翻译：具有多个导电层的半导体器件及其制造方法
公开(公告)号：US4984055A
公开(公告)日：1991-01-08
申请号：US267103
申请日：1988-11-07
申请人： Yoshinori Okumura , Atsuhiro Fujii , Masao Nagatomo , Hiroji Ozaki , Wataru Wakamiya , Takayuki Matsukawa
发明人： Yoshinori Okumura , Atsuhiro Fujii , Masao Nagatomo , Hiroji Ozaki , Wataru Wakamiya , Takayuki Matsukawa
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L23/522 , H01L27/10 , H01L27/108
CPC分类号： H01L23/485 , H01L23/522 , H01L2924/0002
摘要： A semiconductor device having a plurality of conductive layers is disclosed. The device has first level conductors (9) formed spaced apart on a semiconductor substrate (1). The semiconductor substrate (1) is provided with impurity diffusion regions (11) in its major surface between adjacent first level conductors (9). A triple layer insulation formed of a pair of oxide layers (12, 14) and an silicon oxide layer (13) sandwiched between the oxide layers (12, 14) covers the semiconductor substrate (1) and the first level conductors (9) thereon. At least one contact hole (15) is formed to extend through the triple layer insulation to either the impurity diffusion region (11) in the semiconductor substrate (1) or the first level conductor (9) on the semiconductor substrate (1). A second level conductor (16, 17) is provided on the triple layer insulation and on the inner surrounding wall of the contact hole (15). Each of the three insulating layers in the triple layer insulation has its hole-defining surface exposed at the contact hole (15) flush with or displaced laterally into the contact hole (15) away from a corresponding hole-defining exposed surface of the next overlying insulating layer.
摘要翻译：公开了具有多个导电层的半导体器件。该器件具有在半导体衬底（1）上间隔开形成的第一级导体（9）。半导体衬底（1）在相邻的第一层导体（9）之间的主表面上设置有杂质扩散区（11）。由一对氧化物层（12,14）和夹在氧化物层（12,14）之间的氧化硅层（13）形成的三层绝缘体覆盖在其上的半导体衬底（1）和第一层导体（9）。形成至少一个接触孔（15），以通过三层绝缘体延伸到半导体衬底（1）中的杂质扩散区域（11）或半导体衬底（1）上的第一级导体（9）中。在三层绝缘体和接触孔（15）的内周围壁上设置有二级导体（16,17）。三层绝缘体中的三个绝缘层中的每一个具有其露出在接触孔（15）处的孔限定表面，该接触孔（15）与接触孔（15）平齐地或相对地偏离接触孔（15），远离与下一个上覆的相应的孔限定的暴露表面绝缘层。

33. 发明授权

US4956692A Semiconductor device having an isolation oxide film 失效
标题翻译：具有隔离氧化膜的半导体器件
公开(公告)号：US4956692A
公开(公告)日：1990-09-11
申请号：US266704
申请日：1988-11-03
申请人： Hiroji Ozaki , Masahiro Yoneda , Ikuo Ogoh , Yoshinori Okumura , Wataru Wakamiya , Masao Nagatomo
发明人： Hiroji Ozaki , Masahiro Yoneda , Ikuo Ogoh , Yoshinori Okumura , Wataru Wakamiya , Masao Nagatomo
IPC分类号： H01L27/10 , H01L21/31 , H01L21/334 , H01L21/76 , H01L21/762 , H01L21/8242 , H01L27/108
CPC分类号： H01L29/66181 , H01L21/76205 , H01L27/10829
摘要： Two trenches are formed at a predetermined distance on a main surface of a semiconductor substrate. An oxide film and a nitride film are successively formed on the main surface of the semiconductor including the inner surfaces of the trenches. After a resist is formed over the whole surface including the inner surfaces of the trenches, the resist is patterned to expose a portion of the nitride film on a side surface of each trench. The exposed portions of the nitride film are removed by using the patterned resist as a mask and thermal oxidation is applied. Then, an isolation oxide film is formed on a region between the trenches and an end of a bird's beak is located on a side surface of each trench and is connected to the oxide film formed in each trench.
摘要翻译：在半导体衬底的主表面上以预定距离形成两个沟槽。在包括沟槽的内表面的半导体的主表面上依次形成氧化物膜和氮化物膜。在包括沟槽的内表面的整个表面上形成抗蚀剂之后，将抗蚀剂图案化以在每个沟槽的侧表面上暴露出氮化膜的一部分。通过使用图案化的抗蚀剂作为掩模去除氮化物膜的暴露部分并施加热氧化。然后，在沟槽之间的区域上形成隔离氧化膜，并且鸟嘴的端部位于每个沟槽的侧表面上并连接到形成在每个沟槽中的氧化膜。

34. 发明授权

US5834817A Field effect transistor with a shaped gate electrode 失效
公开(公告)号：US5834817A
公开(公告)日：1998-11-10
申请号：US983931
申请日：1992-12-01
申请人： Shinichi Satoh , Hiroji Ozaki , Takahisa Eimori
发明人： Shinichi Satoh , Hiroji Ozaki , Takahisa Eimori
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/43 , H01L29/78
CPC分类号： H01L29/66598 , H01L21/28061 , H01L21/28114 , H01L29/42376 , H01L29/6659
摘要： A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source.multidot.drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.

35. 发明授权

US5459344A Stacked capacitor type semiconductor memory device and manufacturing method thereof 失效
标题翻译：叠层电容器型半导体存储器件及其制造方法
公开(公告)号：US5459344A
公开(公告)日：1995-10-17
申请号：US727783
申请日：1991-07-10
申请人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
发明人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/02 , H01L27/10 , H01L27/108 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10817
摘要： A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.
摘要翻译：根据本发明的半导体存储器件包括具有一个晶体管和一个堆叠电容器的存储单元。堆叠的电容器堆叠在半导体衬底的表面上。此外，层叠电容器具有通过绝缘层在栅电极和字线上延伸的结构。电容器的下电极层具有各种凹凸形状，即台阶部分和形成在其表面上的突出部分。这些形状通过采用各种蚀刻工艺制成。下电极层在其上形成有各种凹凸形状，从而能够提高电容器的表面积和电容。

36. 发明授权

US5288661A Semiconductor device having bonding pad comprising buffer layer 失效
标题翻译：具有包括缓冲层的焊盘的半导体器件
公开(公告)号：US5288661A
公开(公告)日：1994-02-22
申请号：US796976
申请日：1991-11-25
申请人： Shinichi Satoh , Hiroji Ozaki , Hiroshi Kimura , Wataru Wakamiya , Yoshinori Tanaka
发明人： Shinichi Satoh , Hiroji Ozaki , Hiroshi Kimura , Wataru Wakamiya , Yoshinori Tanaka
IPC分类号： H01L21/60 , H01L23/485 , H01L21/28
CPC分类号： H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/45124 , H01L2224/45144 , H01L2224/48247 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/85205 , H01L24/45 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01068 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/3025
摘要： A semiconductor device according to the present invention comprises a substrate (4) in a periphery of which formed are elements isolating regions. A bonding pad (3) is formed above the elements isolating region with an isolation layer (7) provided therebetween. An underlying layer (12) having a buffering function is formed on a surface of the bonding pad and the semiconductor substrate. In case the elements isolating region is formed of LOCOS film (30), the underlying layer is formed between the bonding pad and the LOCOS film. In case the elements isolating region is of a field-shield structure (13, 14), the underlying layer (12) is formed by separating a part of a gate electrode layer (14) of the field shield into an island. The underlying layer buffers external force applied on the bonding pad in a bonding processing to prevent generation of cracks in the semiconductor layer.
摘要翻译：根据本发明的半导体器件包括其周围形成有元件隔离区的衬底（4）。在元件隔离区域的上方形成有焊盘（3），隔离层（7）设置在它们之间。在接合焊盘和半导体衬底的表面上形成具有缓冲功能的下层（12）。在元件隔离区域由LOCOS膜（30）形成的情况下，在焊盘和LOCOS膜之间形成下层。在元件隔离区域是场屏蔽结构（13,14）的情况下，通过将场屏蔽体的栅极电极层（14）的一部分分离成岛来形成下层（12）。底层在接合处理中缓冲施加在接合焊盘上的外力，以防止在半导体层中产生裂缝。

37. 发明授权

US5278437A Stacked capacitor type semiconductor memory device and manufacturing method thereof 失效
标题翻译：叠层电容器型半导体存储器件及其制造方法
公开(公告)号：US5278437A
公开(公告)日：1994-01-11
申请号：US947615
申请日：1992-09-21
申请人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
发明人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/02 , H01L27/10 , H01L27/108 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10817
摘要： A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.
摘要翻译：根据本发明的半导体存储器件包括具有一个晶体管和一个堆叠电容器的存储单元。堆叠的电容器堆叠在半导体衬底的表面上。此外，层叠电容器具有通过绝缘层在栅电极和字线上延伸的结构。电容器的下电极层具有各种凹凸形状，即台阶部分和形成在其表面上的突出部分。这些形状通过采用各种蚀刻工艺制成。下电极层在其上形成有各种凹凸形状，从而能够提高电容器的表面积和电容。

38. 发明授权

US5164803A CMOS semiconductor device with an element isolating field shield 失效
标题翻译： CMOS半导体器件与元件隔离场屏蔽
公开(公告)号：US5164803A
公开(公告)日：1992-11-17
申请号：US657261
申请日：1991-02-19
申请人： Hiroji Ozaki , Shinichi Satoh , Takahisa Eimori , Wataru Wakamiya , Yoshinori Tanaka
发明人： Hiroji Ozaki , Shinichi Satoh , Takahisa Eimori , Wataru Wakamiya , Yoshinori Tanaka
IPC分类号： H01L21/76 , H01L21/765 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0928 , H01L21/765 , H01L27/088
摘要： A semiconductor device comprises an MOSFET (13) comprising a switching gate electrode (5) and a field shield MOS structure (11) formed on an element isolating region of a semiconductor substrate (1) and performs the element isolation by applying a bias voltage to the field shield (9). The field shield (9) is provided on the element isolating region of the semiconductor substrate (1) through an insulating film (8). A sidewall spacer (12) having its width set such that the field shield (9) may be an offset gate is formed on the side portion of the field shield (9). Then, source and drain layers (6) are formed on the main surface of the semiconductor substrate (1) so as not to overlap with the field shield (9). According to the semiconductor device, since the field shield (9) is the offset gate, it is possible to set high the threshold value on a parasitic MOS transistor and miniaturize the elements.
摘要翻译：半导体器件包括MOSFET（13），其包括形成在半导体衬底（1）的元件隔离区上的开关栅极（5）和场屏蔽MOS结构（11），并通过施加偏置电压来执行元件隔离场地屏蔽（9）。场屏蔽（9）通过绝缘膜（8）设置在半导体衬底（1）的元件隔离区上。侧壁间隔件（12）的宽度被设定为使得场屏蔽（9）可以是偏移栅极，形成在场屏蔽（9）的侧部上。然后，在半导体衬底（1）的主表面上形成源极和漏极层（6），以便不与场屏蔽（9）重叠。根据半导体器件，由于场屏蔽（9）是偏移栅极，因此可以将寄生MOS晶体管上的阈值设定为高，并且使元件小型化。

39. 发明授权

US5159417A Semiconductor device having short channel field effect transistor with extended gate electrode structure and manufacturing method thereof 失效
标题翻译：具有扩展门电极结构的短路通道场效应晶体管的半导体器件及其制造方法
公开(公告)号：US5159417A
公开(公告)日：1992-10-27
申请号：US678636
申请日：1991-04-02
申请人： Hiroji Ozaki
发明人： Hiroji Ozaki
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/66659 , H01L29/7831
摘要： A semiconductor device comprises a semiconductor substrate (1), a source region (5) and a drain region (6) a first gate electrode (4), a second gate electrode (8), an insulator layer (9) and a conductor layer (10). The semiconductor substrate (1) contains impurity of a first conductive type in a predetermined concentration. The source region (5) and the drain region (6) are formed and spaced on the main surface of the semiconductor substrate (1), and contains impurity of a second conductive type in a concentration which is 10 to 10.sup.3 times as large as that of the impurity of the first conductive type. The first gate electrode (4) is located between the source and drain regions (5) and (6) and formed on the main surface of the semiconductor substrate (1) with an insulating film (3) therebetween. The second gate electrode (8) is formed to have portions overlapping a portion of the source region (5) and a portion of the first gate electrode (4) with an insulating film (7 ) therebetween. The insulator layer (9) has an opening (20) through which surfaces of at least the first and second gate electrodes (4) and (8) are exposed. The conductor layer (10) electrically contacts the surfaces of the first and second gate electrodes (4) and (8) through the opening (20). The field effect transistor has a high current drive capacity and a high resistance to the hot carriers. The field effect transistor can have a gate length of a quarter micron order.
摘要翻译：半导体器件包括半导体衬底（1），源极区（5）和漏极区（6），第一栅电极（4），第二栅电极（8），绝缘体层（9）和导体层（10）。半导体衬底（1）含有预定浓度的第一导电类型的杂质。源极区域（5）和漏极区域（6）在半导体衬底（1）的主表面上形成并间隔开，并且含有浓度为10至103倍的浓度的第二导电类型的杂质的第一导电类型的杂质。第一栅极（4）位于源极和漏极区域（5）和（6）之间并且在半导体衬底（1）的主表面上形成有绝缘膜（3）。第二栅电极（8）形成为具有与源极区（5）的一部分和第一栅电极（4）的一部分之间的绝缘膜（7）重叠的部分。绝缘体层（9）具有至少第一和第二栅电极（4）和（8）的表面露出的开口（20）。导体层（10）通过开口（20）与第一和第二栅电极（4）和（8）的表面电接触。场效应晶体管具有高电流驱动能力和对热载流子的高电阻。场效应晶体管可以具有四分之一微米级的栅极长度。

40. 发明授权

US5067000A Semiconductor device having field shield isolation 失效
标题翻译：具有场屏蔽隔离的半导体器件
公开(公告)号：US5067000A
公开(公告)日：1991-11-19
申请号：US391008
申请日：1989-08-09
申请人： Takahisa Eimori , Shinichi Satoh , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka
发明人： Takahisa Eimori , Shinichi Satoh , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka
IPC分类号： H01L21/76 , H01L21/765 , H01L29/78
CPC分类号： H01L21/765
摘要： A first conductor for a field shield and a first insulating film are sequentially formed in a predetermined shape on a major surface of a P-type semiconductor substrate through an insulating film. A third insulating film is formed over the semiconductor substrate so as to cover the first conductor and a second insulating film thereon. The third insulating film is anisotropically etched, so that a sidewall insulating film is formed on sidewalls of the first conductor. Second and third conductors respectively serving as gate electrodes of field effect transistors are formed through a fourth insulating film. N-type impurities are implanted into the major surface of the semiconductor substrate utilizing as masks the first insulating film, the sidewall oxide film, the second conductor and the third conductor and are diffused, to form impurity regions. Since the sidewall oxide film is thick, the impurity regions are not overlapped even by diffusion with a portion where the first conductor is projected on the semiconductor substrate. Thus, a threshold voltage of a field shield transistor comprising the first conductor and the impurity regions on both sides thereof is raised, so that isolation characteristics of the field shield is improved.
摘要翻译：用于场屏蔽和第一绝缘膜的第一导体通过绝缘膜在P型半导体衬底的主表面上依次形成为预定形状。在半导体衬底上形成第三绝缘膜，以覆盖第一导体和第二绝缘膜。第三绝缘膜被各向异性地蚀刻，从而在第一导体的侧壁上形成侧壁绝缘膜。分别用作场效晶体管的栅极的第二和第三导体通过第四绝缘膜形成。利用第一绝缘膜，侧壁氧化物膜，第二导体和第三导体作为掩模将N型杂质注入到半导体衬底的主表面中，并扩散，形成杂质区。由于侧壁氧化物膜厚，因此即使通过第一导体投射在半导体基板上的部分的扩散也不会使杂质区域重叠。因此，包括第一导体和其两侧的杂质区域的场屏蔽晶体管的阈值电压升高，从而提高了场屏蔽的隔离特性。

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