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31. 发明授权

US06532567B2 Method and apparatus of Viterbi detection for trellis-code 失效
标题翻译：网格码维特比检测方法及装置
公开(公告)号：US06532567B2
公开(公告)日：2003-03-11
申请号：US09422494
申请日：1999-10-21
申请人： Hiroyuki Ino
发明人： Hiroyuki Ino
IPC分类号： G06F1100
CPC分类号： G11B20/10046 , G11B20/10055 , G11B20/10222 , G11B20/10287 , G11B20/10296 , G11B20/10425 , G11B20/18 , G11B2020/1287 , H03M13/256 , H03M13/41 , H03M13/4107 , H03M13/6343
摘要： A method and apparatus for Viterbi detection to detect a code sequence containing a sync word, from an output sequence on a transmission path, by using a trellis detection that has a time-variant structure. The apparatus comprising a base counter for measuring time during the trellis detection, a comparator for comparing the time when the sync word is detected and outputting a coincidence/non-coincidence signal, and a selector for selecting either an output of an ACS (Add Compare Select) circuit or a predetermined initial metric value. The likelihood of a state in which the sync word starts or ends in the trellis detection is initialized only if the time the sync word is detected does not coincide with a time extrapolated before the sync word is detected.
摘要翻译：一种用于维特比检测的方法和装置，通过使用具有时变结构的网格检测，从传输路径上的输出序列检测包含同步字的码序列。该装置包括用于在网格检测期间测量时间的基本计数器，用于比较同步字被检测的时间并输出一致/非重合信号的比较器，以及用于选择ACS的输出（添加比较选择）电路或预定的初始度量值。仅在检测到同步字的时间与在检测到同步字之前外推的时间不一致的情况下才初始化在网格检测中同步字开始或结束的状态的可能性。

32. 发明授权

US06288657B1 Encoding apparatus and method, decoding apparatus and method, and distribution media 失效
标题翻译：编码装置和方法，解码装置和方法以及分发媒体
公开(公告)号：US06288657B1
公开(公告)日：2001-09-11
申请号：US09409799
申请日：1999-09-30
申请人： Hiroyuki Ino
发明人： Hiroyuki Ino
IPC分类号： H03M116
CPC分类号： H03M5/06
摘要： The subtracter performs subtraction processing between a pointer outputted from the pointer register and code words candidate outputted from the code word count storing circuit, and in accordance with whether the result is negative or positive, determines the code words of input data words. Code word candidates stored in the code word count storing circuit are created according to a finite-state transition diagram stored in the state transition storing circuit. An encoder and a decoder are thus made compact and faster.
摘要翻译：减法器在从指针寄存器输出的指针和从代码字计数存储电路输出的代码字候选之间执行减法处理，并且根据结果是否定还是正的，确定输入数据字的代码字。根据存储在状态转换存储电路中的有限状态转移图来创建存储在代码字计数存储电路中的代码字候选。因此，编码器和解码器紧凑且更快。

33. 发明授权

US5946329A Viterbi decoding method and viterbi decoder 失效
标题翻译：维特比解码方法和维特比解码器
公开(公告)号：US5946329A
公开(公告)日：1999-08-31
申请号：US786209
申请日：1997-01-21
申请人： Toshihiko Hirose , Hiroyuki Ino
发明人： Toshihiko Hirose , Hiroyuki Ino
IPC分类号： H03M13/23 , G11B20/10 , H03M13/41 , G06F11/10
CPC分类号： H03M13/6502 , G11B20/10009 , H03M13/41
摘要： A Viterbi decoding method and decoder are provided for achieving a faster operation than the prior art. The Viterbi decoding method and decoder are arranged to determine the most approximate path on two-state state metrics and decode the data on the most approximate path. The Viterbi decoder includes registers 2 and 3 for reading two pieces of sample data, an adder 14 for adding two pieces of sample data read by the registers 2 and 3, and an arrangement located after the adder 14 for determining a path of each state transition by comparing the added result with a given identification of -1, 0 or 1.
摘要翻译：提供维特比解码方法和解码器以实现比现有技术更快的操作。维特比解码方法和解码器被布置成确定两状态状态度量上的最近路径，并对最近路径上的数据进行解码。维特比解码器包括用于读取两个采样数据的寄存器2和3，用于加上由寄存器2和3读取的两个采样数据的加法器14以及位于加法器14之后的用于确定每个状态转换的路径的配置通过比较添加的结果与-1,0或1的给定标识。

34. 发明授权

US5638063A Code modulation method, code demodulation method, and code detection method 失效
标题翻译：码调制方法，码解调方法和码检测方法
公开(公告)号：US5638063A
公开(公告)日：1997-06-10
申请号：US579002
申请日：1995-12-27
申请人： Hiroyuki Ino
发明人： Hiroyuki Ino
IPC分类号： H04N19/00 , G11B20/10 , G11B20/14 , G11B20/18 , H03M5/14 , H03M7/14 , H04N19/423 , H04N19/59 , H04N19/65 , H03M7/00
CPC分类号： G11B20/10083 , G11B20/10009 , H03M5/145
摘要： Carrying out DSV control with a PR(1, 1) while making free distance larger and path memory length shorter. "3.times.3" states are arranged in a plane defined by a horizontal axis and a vertical axis, with a code 11 being allotted to correspond to rightward transitions along the horizontal axis and a code 00 being allotted to correspond to leftward transitions. A code 01 is allotted to upward transitions along the vertical axis and a code 10 is allotted to correspond to downward transitions. Codes obtained in the case of transitions from a start point taken as one of the states 1, 3, 5 or 7, to the states 1, 3, 5 or 7 taken as end points through the other five states are used as codes after conversion. For example, the codes 01, 01, 11, 00, 10 and 10 are obtained from a transition through state 1, state 4, state 7, state 8, state 7, state 4 and state 1.
摘要翻译：使PR（1，1）执行DSV控制，同时使空闲距离更大，路径内存长度更短。 “3×3”状态被布置在由水平轴和垂直轴定义的平面中，其中分配有代码11以对应于沿着水平轴的向右过渡，并且分配代码00以对应于向左的转变。代码01被分配给沿着垂直轴的向上转换，并且分配代码10以对应于向下转换。在从作为状态1,3,5或7之一的起点转换到作为其他五种状态的端点的状态1,3,5或7的情况下获得的代码被用作转换后的代码。例如，通过状态1，状态4，状态7，状态8，状态7，状态4和状态1的转换获得代码01，01，11，00，10和10。

35. 发明授权

US4862297A Apparatus for reproducing a digital signal without employing tracking signals 失效
标题翻译：用于在不使用跟踪信号的情况下再现数字信号的装置
公开(公告)号：US4862297A
公开(公告)日：1989-08-29
申请号：US152821
申请日：1988-02-05
申请人： Tadashi Fukami , Hiroyuki Ino
发明人： Tadashi Fukami , Hiroyuki Ino
IPC分类号： G11B20/18
CPC分类号： G11B20/1809
摘要： A reproducing apparatus for reproducing blocks from a recording medium on which a plurality of signal blocks are recorded on plural recording tracks, uses a rotary head which is rotated at a speed equal to at least twice the normal speed. Error detection of a reproduced signal is performed for each signal block, and a detection signal and a reproduced signal of the corresponding signal block are written into a memory. If the detection signal indicates that no error is detected, the reproduced signal from the corresponding signal block is prevented from being written again into the memory. A reproduced track address signal and a reference track address signal are compared, and in accordance with the comparison result, translation of the recording medium is controlled.

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