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31. 发明申请

US20080266965A1 NONVOLATILE SEMICONDUCTOR MEMORY HAVING PLURAL DATA STORAGE PORTIONS FOR A BIT LINE CONNECTED TO MEMORY CELLS 审中-公开
标题翻译：具有连接到存储单元的位线的多个数据存储部分的非易失性半导体存储器
公开(公告)号：US20080266965A1
公开(公告)日：2008-10-30
申请号：US12163676
申请日：2008-06-27
申请人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
发明人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/1051 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/5649 , G11C2211/565 , G11C2216/14
摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
摘要翻译：具有三个以上值的数据以非易失性方式存储在存储单元中。数据电路具有多个存储电路。多个存储电路中的一个是锁存电路。多个存储电路中的另一个是电容器。锁存电路和电容器用于临时存储具有两位或更多位的程序/读数据。如果由于泄漏引起的数据变化导致程序，则使用锁存电路来刷新由电容器保持的数据。结果，即使使用多级数据，数据电路也不会变大。

32. 发明授权

US07388790B2 Semiconductor memory device and dynamic latch refresh method thereof 有权
标题翻译：半导体存储器件及其动态锁存刷新方法
公开(公告)号：US07388790B2
公开(公告)日：2008-06-17
申请号：US11510733
申请日：2006-08-28
申请人： Hiroshi Maejima , Noboru Shibata , Katsuaki Isobe
发明人： Hiroshi Maejima , Noboru Shibata , Katsuaki Isobe
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/0483 , G11C29/70 , G11C29/832 , G11C2211/565 , H01L27/105 , H01L27/115
摘要： A semiconductor integrated circuit device includes dynamic latches, switch circuit, capacitor, first static latch, and first transfer gate. In refreshing data of the dynamic latches, data stored in the first static latch is moved to the second node through the first transfer gate and saved. The data of the dynamic latch is bootstrapped. The bootstrapped data is transferred to the first node to distribute charges, thereby setting the potential of the first node. The set potential is written back to the dynamic latch to refresh it. The saved data of the second node is moved to the first node through the first transfer gate and written back to the first static latch.
摘要翻译：半导体集成电路器件包括动态锁存器，开关电路，电容器，第一静态锁存器和第一传输门。在动态锁存器的刷新数据中，存储在第一静态锁存器中的数据通过第一传送门移动到第二节点并被保存。动态锁存器的数据被自举。自举数据被传送到第一节点以分配费用，从而设置第一节点的电位。设置电位被写回到动态锁存器来刷新它。第二节点的保存数据通过第一传输门移动到第一节点并写回到第一静态锁存器。

33. 发明授权

US07366018B2 Semiconductor memory device capable of setting a negative threshold voltage 有权
标题翻译：能够设定负阈值电压的半导体存储器件
公开(公告)号：US07366018B2
公开(公告)日：2008-04-29
申请号：US11300364
申请日：2005-12-15
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/30 , G11C16/3454
摘要： In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potentials of the word lines and bit lines. The control circuit, when reading data from the memory cell connected to a first one of the bit lines, supplies a first voltage to a second bit line provided next to the first bit line and to a source line of the memory cell array.
摘要翻译：在存储单元阵列中，连接到字线和位线的多个存储单元被布置成矩阵。控制电路控制字线和位线的电位。控制电路当从连接到第一位线的存储单元读取数据时，将第一电压提供给位于第一位线旁边的第二位线和存储单元阵列的源极线。

34. 发明授权

US07349249B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07349249B2
公开(公告)日：2008-03-25
申请号：US11389083
申请日：2006-03-27
申请人： Mitsuaki Honma , Noboru Shibata , Kazunori Kanebako
发明人： Mitsuaki Honma , Noboru Shibata , Kazunori Kanebako
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C2211/5621 , G11C2211/5641 , G11C2211/5646
摘要： A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell storing data defined by threshold voltage thereof, wherein the memory cell array includes first and second areas; the first area stores multi-value data written with plural write steps; and the second area stores binary data defined by first and second logic states, threshold levels of which are controlled through the plural write steps adapted to the multi-value data write.
摘要翻译：半导体存储器件包括其中布置有存储器单元的存储单元阵列，每个存储器单元存储由其阈值电压定义的数据，其中存储单元阵列包括第一和第二区域; 第一区域存储用多个写入步骤写入的多值数据; 并且第二区域存储由第一和第二逻辑状态定义的二进制数据，其阈值级别通过适于多值数据写入的多个写入步骤来控制。

35. 发明授权

US07342825B2 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells 有权
公开(公告)号：US07342825B2
公开(公告)日：2008-03-11
申请号：US11690674
申请日：2007-03-23
申请人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
发明人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/1051 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/5649 , G11C2211/565 , G11C2216/14
摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

36. 发明授权

US07315471B2 Semiconductor memory device for storing multivalued data 有权
标题翻译：用于存储多值数据的半导体存储器件
公开(公告)号：US07315471B2
公开(公告)日：2008-01-01
申请号：US11469279
申请日：2006-08-31
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621 , G11C2211/5646 , G11C2211/5648 , G11C2216/14
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.
摘要翻译：数据存储电路以一一对应的方式连接到位线。写电路将第一页上的数据写入由字线同时选择的多个第一存储单元。此后，写电路将第二页上的数据写入多个第一存储单元。然后，写入电路将第一和第二页面上的数据写入与位线方向相邻的第一存储单元的第二存储单元。

37. 发明申请

US20070285980A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20070285980A1
公开(公告)日：2007-12-13
申请号：US11737373
申请日：2007-04-19
申请人： Takahiro SHIMIZU , Noboru Shibata
发明人： Takahiro SHIMIZU , Noboru Shibata
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C2211/5641 , G11C2211/5643
摘要： A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region.
摘要翻译：本发明的半导体存储器件包括存储单元阵列，该存储单元阵列包括具有多个存储单元的第一区域，每个存储器单元能够存储n位数据（n为自然数）和具有多个存储单元的第二区域每个能够存储k比特数据（k> n：k是自然数），包括多个数据高速缓存的数据存储电路，以及控制该存储单元阵列和数据存储电路的控制电路将从第一区域中的k / n个存储单元读取的k位数据存储到数据存储电路中的方式，并将k位数据存储到第二区域中的存储单元中。

38. 发明申请

US20070280017A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070280017A1
公开(公告)日：2007-12-06
申请号：US11772271
申请日：2007-07-02
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

39. 发明授权

US07295469B2 Nonvolatile semiconductor memory device with a ROM block settable in a write/erase inhibit mode 有权
标题翻译：具有可设置为写/擦除禁止模式的ROM块的非易失性半导体存储器件
公开(公告)号：US07295469B2
公开(公告)日：2007-11-13
申请号：US11530340
申请日：2006-09-08
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/22
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

40. 发明申请

US20070253272A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF EXECUTING HIGH-SPEED READ 有权
标题翻译：可执行高速读取的半导体存储器件
公开(公告)号：US20070253272A1
公开(公告)日：2007-11-01
申请号：US11737413
申请日：2007-04-19
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C8/00
CPC分类号： G11C16/12 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/565
摘要： A plurality of memory cells are arranged in a memory cell array. The plurality of memory cells are connected to a plurality of word lines and a plurality of bit lines. A plurality of source lines are disposed along the plurality of bit lines. The plurality of source lines are connected respectively to sources of the plurality of memory cells at a time of data read.
摘要翻译：多个存储单元布置在存储单元阵列中。多个存储单元连接到多个字线和多个位线。多条源极线沿多条位线配置。多个源极线在数据读取时分别连接到多个存储单元的源极。

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