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31. 发明授权

US08299805B2 Evaluation device and evaluation system evaluating whether a required output is made from the device to be evaluated 有权
标题翻译：评估装置和评估系统评估是否从要评估的装置进行所需的输出
公开(公告)号：US08299805B2
公开(公告)日：2012-10-30
申请号：US12018664
申请日：2008-01-23
申请人： Tomihiro Mugitani , Takashi Kobayashi , Tatsuhiko Nakajima
发明人： Tomihiro Mugitani , Takashi Kobayashi , Tatsuhiko Nakajima
IPC分类号： G01R27/02
CPC分类号： H04M1/24
摘要： An evaluation device 20 comprises a circuit element comprising respective pairs of inputs and outputs including several capacitances 25a-25c and resistances 26a-26d, one end of each being connected to both ends of the capacitances 25a-25c, wherein a resistance value of a signal input side is generally equal to that of a signal output side. The evaluation device 20 is further provided with a connecting terminal with an output device 10 for outputting signals to a device to be evaluated 30 on the signal input side, and is provided with a connecting terminal with the device to be evaluated 30 on the signal output side.
摘要翻译：评估装置20包括电路元件，其包括相应的输入和输出对，该对输入和输出包括若干电容25a-25c和电阻26a-26d，其一端连接到电容25a-25c的两端，其中信号的电阻值输入侧通常等于信号输出侧的输入侧。评估装置20还具有连接端子，其具有用于在信号输入侧向待评估装置30输出信号的输出装置10，并且在信号输出端上设置有待评估装置30的连接端子侧。

32. 发明授权

US08278700B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08278700B2
公开(公告)日：2012-10-02
申请号：US13072211
申请日：2011-03-25
申请人： Taro Osabe , Tomoyuki Ishii , Kazuo Yano , Takashi Kobayashi
发明人： Taro Osabe , Tomoyuki Ishii , Kazuo Yano , Takashi Kobayashi
IPC分类号： H01L29/792
CPC分类号： H01L27/11521 , B82Y10/00 , G11C16/0433 , G11C16/0458 , G11C16/0483 , G11C16/0491 , G11C16/10 , G11C16/26 , G11C2216/06 , H01L27/115 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.
摘要翻译：为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过细胞水平。

33. 发明授权

US08214982B2 Method of fabricating piezoelectric vibrating pieces 失效
标题翻译：制造压电振动片的方法
公开(公告)号：US08214982B2
公开(公告)日：2012-07-10
申请号：US12360435
申请日：2009-01-27
申请人： Takashi Kobayashi
发明人： Takashi Kobayashi
IPC分类号： H04R17/10 , H01L41/047
CPC分类号： H03H9/1021 , H03H3/02 , H03H9/0547 , H03H9/21 , Y10T29/42 , Y10T29/49147 , Y10T29/49155 , Y10T29/49574
摘要： To carry out frequency adjustment easily, accurately and efficiently without being influenced by a size of a piezoelectric vibrating piece and achieve low cost formation and promotion of maintenance performance, there is provided a method of fabricating a piezoelectric vibrating piece which is a method of fabricating a piezoelectric vibrating piece having a piezoelectric vibrating plate 11, a pair of exciting electrodes 12, 13, and a pair of mount electrodes 15, 16 by utilizing a wafer S, the method including an outer shape forming step of forming a frame portion S1 at a wafer and forming a plurality of piezoelectric plates at the frame portion to be connected thereto by way of a connecting portion 11a, an electrode forming step of forming pairs of exciting electrodes and pairs of mount electrodes respectively at the plurality of piezoelectric plates and forming a common electrode S2 respectively electrically connected to a plurality of the pairs of mount electrodes 15 on one side by way of the connecting portion, a frequency adjusting step of adjusting a frequency of the piezoelectric plate by applying a drive voltage between the common electrode and the mount electrode 16 on other side, and a cutting step of fragmenting the plurality of piezoelectric plates.
摘要翻译：为了容易地，准确而有效地进行频率调整而不受压电振动片的尺寸的影响，并且实现低成本形成和提高维护性能，提供了一种制造压电振动片的方法，该方法是制造具有压电振动板11的压电振动片，利用晶片S的一对激励电极12,13和一对安装电极15,16，该方法包括：外形形成步骤，以在晶片，并通过连接部分11a在框架部分形成多个压电板，电极形成步骤分别在多个压电板上形成一对激励电极和一对安装电极，并形成共同的电极S2分别电连接到一对侧的多对安装电极15上连接部分的ay;频率调节步骤，通过在公共电极和另一侧的安装电极16之间施加驱动电压来调节压电板的频率，以及分割多个压电板的切割步骤。

34. 发明授权

US08174229B2 Sample stage apparatus and method of controlling the same 有权
标题翻译：样品台装置及其控制方法
公开(公告)号：US08174229B2
公开(公告)日：2012-05-08
申请号：US12420358
申请日：2009-04-08
申请人： Masashi Fujita , Shuichi Nakagawa , Takashi Kobayashi
发明人： Masashi Fujita , Shuichi Nakagawa , Takashi Kobayashi
IPC分类号： B64C17/06
CPC分类号： H01J37/20 , H01J2237/20228 , H01J2237/20285 , H01J2237/20292
摘要： The present invention provides a stage apparatus capable of reducing a positioning time without increasing a positional deviation. A positioning control method of a sample stage apparatus includes: a high-speed movement step of moving a table to a high-speed movement target position at a first movement speed; a positional deviation correcting step of moving the table to a low-speed positioning step start position at a second movement speed that is lower than the first movement speed; a low-speed positioning step of moving the table to a target position at a third movement speed that is lower than the second movement speed. After the low-speed positioning step is completed, a rod connected to a motor returns to its original position to separate a pin of the rod side from a concave portion of the table side.
摘要翻译：本发明提供一种能够在不增加位置偏差的情况下减少定位时间的舞台装置。采样台装置的定位控制方法包括：以第一移动速度将桌子移动到高速移动目标位置的高速移动步骤; 位置偏差校正步骤，以低于第一移动速度的第二移动速度将桌子移动到低速定位步骤开始位置; 低速定位步骤，以低于第二移动速度的第三移动速度将桌子移动到目标位置。在低速定位步骤完成之后，连接到电动机的杆返回到其原始位置，以将杆侧的销与台侧的凹部分开。

35. 发明授权

US08173932B2 Perforation method and perforation apparatus 有权
标题翻译：穿孔法和穿孔装置
公开(公告)号：US08173932B2
公开(公告)日：2012-05-08
申请号：US12178263
申请日：2008-07-23
申请人： Takashi Kobayashi , Akihiro Nemoto , Hiroaki Yamagishi , Katsuyuki Nakajima
发明人： Takashi Kobayashi , Akihiro Nemoto , Hiroaki Yamagishi , Katsuyuki Nakajima
IPC分类号： B23K26/38
CPC分类号： B23K26/18 , B23K26/389
摘要： A perforation method and an perforation apparatus in which a hollow member of a fuel injection nozzle is filled with a filler such as a zirconia ball, and a laser light is applied to the hollow member to form an injection hole while vibrating the zirconia ball using an ultrasonic vibrator. After the injection hole is formed, the laser light is introduced through the injection hole to the inside of the fuel injection nozzle, and thereby is applied to the vibrated zirconia ball.
摘要翻译：一种穿孔方法和穿孔装置，其中燃料喷嘴的中空构件填充有诸如氧化锆球的填料，并且激光被施加到中空构件以形成喷射孔，同时使用超声波振动器。在形成注射孔之后，将激光通过注射孔引入燃料喷嘴的内部，由此施加到振动的氧化锆球上。

36. 发明授权

US08106395B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08106395B2
公开(公告)日：2012-01-31
申请号：US12113923
申请日：2008-05-01
申请人： Shuntaro Machida , Takashi Kobayashi
发明人： Shuntaro Machida , Takashi Kobayashi
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L22/32 , B81C99/0045 , G01R31/2884 , H01L21/78 , H01L2224/05554
摘要： A technique of manufacturing a semiconductor device capable of performing a probe test by a common test apparatus as normal LSI chips even for large-area chips is provided. A chip comprising a device formed on a device area by a semiconductor process and including a plurality of test areas sectioned by chip areas is prepared. Next, pads to be electrically connected to the device are formed at corresponding positions on the respective plurality of test areas. Subsequently, the respective test areas are tested by a same probe card via the plurality of pads.
摘要翻译：提供了即使对于大面积芯片也能够通过普通的测试装置进行探针测试的半导体器件的制造技术。制备包括通过半导体工艺在器件区域上形成并包括由芯片区域划分的多个测试区域的器件的芯片。接下来，在相应的多个测试区域上的相应位置处形成要与该器件电连接的焊盘。随后，通过多个焊盘通过相同的探针卡测试各个测试区域。

37. 发明申请

US20110284817A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110284817A1
公开(公告)日：2011-11-24
申请号：US13109985
申请日：2011-05-17
申请人： Yoshitaka SASAGO , Masaharu Kinoshita , Mitsuharu Tai , Takashi Kobayashi
发明人： Yoshitaka SASAGO , Masaharu Kinoshita , Mitsuharu Tai , Takashi Kobayashi
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/2481 , H01L27/1021 , H01L27/2409 , H01L27/2436 , H01L27/2472
摘要： In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.
摘要翻译：在非易失性半导体存储器件中，提供了一种通过减小作为选择元件的多晶硅二极管的截止电流来减小器件厚度来促进微细加工的技术。形成以低浓度掺杂有杂质并作为电阻可变存储器的选择元件的多晶硅二极管的电场弛豫层的多晶硅层，以被分成两层或多层，例如多晶硅层。以这种方式抑制电场弛豫层中的n型多晶硅层和p型多晶硅层之间的晶粒边界完全透过，从而防止产生流过的漏电流在不增加多晶硅二极管的高度的情况下施加反偏压的晶粒边界。

38. 发明授权

US07969067B2 Ultrasound probe 失效
标题翻译：超声探头
公开(公告)号：US07969067B2
公开(公告)日：2011-06-28
申请号：US12161962
申请日：2006-11-14
申请人： Takanori Aono , Tatsuya Nagata , Katsunori Asafusa , Takashi Kobayashi , Naoya Kanda
发明人： Takanori Aono , Tatsuya Nagata , Katsunori Asafusa , Takashi Kobayashi , Naoya Kanda
IPC分类号： H01L41/08
CPC分类号： G10K11/002 , A61B8/00
摘要： There is provided an ultrasound probe including a first substrate having a silicon substrate and an ultrasound transmit-receive element, an acoustic lens disposed over an upper surface of the first substrate, and a damping layer disposed under the first substrate, in which a second substrate is disposed between a lower surface of the first substrate and an upper surface of the damping layer, and the second substrate is made of a material having approximately the same linear expansion coefficient and acoustic impedance as the silicon substrate of the first substrate. With this structure, it is possible to provide the ultrasound probe which can prevent damage to the silicon substrate due to temperature change and has excellent transmission/reception performance and structure reliability while reducing noise by reflected waves in transmission and reception.
摘要翻译：提供一种超声波探头，其包括具有硅衬底和超声波发射接收元件的第一衬底，设置在第一衬底的上表面上的声透镜，以及设置在第一衬底下方的阻尼层，其中第二衬底设置在第一基板的下表面和阻尼层的上表面之间，第二基板由具有与第一基板的硅基板大致相同的线膨胀系数和声阻抗的材料制成。利用这种结构，可以提供能够防止由于温度变化而损坏硅基板的超声波探头，并且在发送和接收中减少反射波的噪声的同时具有优异的发送/接收性能和结构可靠性。

39. 发明授权

US07939879B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07939879B2
公开(公告)日：2011-05-10
申请号：US11896800
申请日：2007-09-06
申请人： Taro Osabe , Tomoyuki Ishii , Kazuo Yano , Takashi Kobayashi
发明人： Taro Osabe , Tomoyuki Ishii , Kazuo Yano , Takashi Kobayashi
IPC分类号： H01L29/792
CPC分类号： H01L27/11521 , B82Y10/00 , G11C16/0433 , G11C16/0458 , G11C16/0483 , G11C16/0491 , G11C16/10 , G11C16/26 , G11C2216/06 , H01L27/115 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.
摘要翻译：为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过细胞水平。

40. 发明授权

US07879287B2 Hot-rolled steel sheet for high-strength electric-resistance welded pipe having sour-gas resistance and excellent weld toughness, and method for manufacturing the same 有权
标题翻译：具有耐酸气性和优异的焊接韧性的高强度电阻焊管热轧钢板及其制造方法
公开(公告)号：US07879287B2
公开(公告)日：2011-02-01
申请号：US11049836
申请日：2005-02-03
申请人： Takashi Kobayashi , Hiroshi Nakata , Chikara Kami , Toru Inazumi , Shuji Kawamura
发明人： Takashi Kobayashi , Hiroshi Nakata , Chikara Kami , Toru Inazumi , Shuji Kawamura
IPC分类号： C22C38/60 , C22C38/14 , C22C38/12 , C22C38/00 , C21D9/08 , C21D9/52 , C21D8/02
CPC分类号： C21D8/0226 , C22C38/02 , C22C38/04 , C22C38/08 , C22C38/12 , C22C38/16
摘要： A hot-rolled steel sheet for high-strength ERW pipes contains about 0.02% to about 0.06% C; about 0.05% to about 0.50% Si; about 0.5% to about 1.5% Mn; about 0.010% or less P; about 0.0010% or less S; about 0.01% to about 0.10% Al; about 0.01% to about 0.10% Nb; about 0.001% to about 0.025% Ti; about 0.001% to about 0.005% Ca; about 0.003% or less 0; and about 0.005% or less N, and at least one element selected from the group consisting of about 0.01% to about 0.10% V; about 0.01% to about 0.50% Cu; about 0.01% to about 0.50% Ni; and about 0.01% to about 0.50% Mo on the basis of mass. The group of C, Si, Mn, Cu, Ni, Mo, and V and the group of Ca, 0, and S satisfy specific relationships, and the microstructure of the steel sheet is composed of about 95% by volume or more bainitic ferrite.
摘要翻译：用于高强度ERW管的热轧钢板含有约0.02％至约0.06％的C; 约0.05％至约0.50％的Si; 约0.5％至约1.5％的Mn; 约0.010％以下P; 约0.0010％以下S; 约0.01％至约0.10％的Al; 约0.01％至约0.10％的Nb; 约0.001％至约0.025％的Ti; 约0.001％至约0.005％的Ca; 约0.003％以下0; 和约0.005％以下的N，以及选自约0.01％至约0.10％V的至少一种元素; 约0.01％至约0.50％的Cu; 约0.01％至约0.50％的Ni; 和基于质量的约0.01％至约0.50％的Mo。 C，Si，Mn，Cu，Ni，Mo和V组以及Ca，O和S组的组合满足特定关系，钢板的微结构由约95体积％以上的贝氏体铁素体。

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