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    • 31. 发明授权
    • Moving image processor capable of outputting moving image as still image
    • 能够将运动图像作为静止图像输出的运动图像处理器
    • US06618491B1
    • 2003-09-09
    • US09443276
    • 1999-11-18
    • Hideo Abe
    • Hideo Abe
    • G06K900
    • G06F17/30787G06F17/30805G06F17/30843G11B27/28
    • A moving image data fetch section extracts frame images as well as audio information from moving image data and stores them in a frame memory. A feature amount detection section detects the change of a feature amount included in the frame images constituting the moving image data, and an image selection section selects specific frame images based on the detected image changing characteristics or audio changing characteristics. An image processing section selects a frame image having particularly great change of the image or audio data from among the selected frame images as a to-be-processed image and processes the selected image to have a predetermined expression form. A monitor, a printer or the like outputs the specific frame images selected by the image selection section and the frame image selected and processed by the image processing section as still images.
    • 运动图像数据提取部分从运动图像数据中提取帧图像以及音频信息,并将它们存储在帧存储器中。 特征量检测部分检测包括在构成运动图像数据的帧图像中的特征量的变化,并且图像选择部分基于检测到的图像改变特性或音频改变特性来选择特定帧图像。 图像处理部从所选择的帧图像中选择具有特别大的图像或音频数据的变化的帧图像作为待处理图像,并处理所选择的图像以具有预定的表达形式。 监视器,打印机等将由图像选择部选择的特定帧图像和由图像处理部选择并处理的帧图像作为静止图像输出。
    • 32. 发明授权
    • Multiprocessor system with multiple memory buses for access to shared memories
    • 具有多个存储器总线的多处理器系统,用于访问共享存储器
    • US06321284B1
    • 2001-11-20
    • US09268426
    • 1999-03-12
    • Akio ShinoharaHideo AbeKatsuichi Ohara
    • Akio ShinoharaHideo AbeKatsuichi Ohara
    • G06F1336
    • G06F13/1605G06F13/1663
    • A data processing system having one or more processor modules and a plurality of shared memory busses to increase its total system performance. Processor modules send bus requests to a bus arbiter, when they attempt to make access to shared memories or memory-mapped peripheral control modules. When such memory access requests are received, the bus arbiter checks the availability of each bus that will be used to reach the requested memories, and send bus grant signals to the requesting processor modules after resolving conflicts, if any. Since the system provides separate paths to reach the individual shared memories, two or more processor modules can be granted their access requests at the same time.
    • 具有一个或多个处理器模块和多个共享存储器总线的数据处理系统,以增加其总系统性能。 处理器模块在总线仲裁器尝试访问共享存储器或内存映射外设控制模块时,将总线请求发送到总线仲裁器。 当接收到这样的存储器访问请求时,总线仲裁器检查将用于到达所请求的存储器的每个总线的可用性,并且在解决冲突(如果有的话)之后向发出请求的处理器模块发送总线授权信号。 由于系统提供单独的路径以到达各个共享存储器,因此可以同时授予两个或多个处理器模块的访问请求。
    • 33. 发明授权
    • Semiconductor memory circuit having bit clear and/or register initialize
function
    • 具有位清除和/或寄存器初始化功能的半导体存储电路
    • US5402381A
    • 1995-03-28
    • US894434
    • 1992-06-05
    • Satoru SonobeHideo Abe
    • Satoru SonobeHideo Abe
    • G06F15/78G11C7/20G11C11/41G11C7/00
    • G11C7/20
    • A semiconductor memory circuit includes a plurality of memory cells arranged in an array form, a plurality of data lines for reading and writing data, a plurality of address lines each for transferring an address signal that specifies a corresponding specific memory cell, a control unit for controlling reading and writing of the data, a plurality of data input and data output terminals for inputting and outputting the data, a write enable signal input terminal to which a write enable signal for permitting writing of the data is applied, and at least one control signal input terminal to which either a cell clear signal for clearing the data stored or a cell initialization signal for performing the initialization of the data is applied. Data reading, data writing and data clearing or data initializing are performed through the plurality of data lines and the plurality of address lines. The hardware area to be occupied is reduced due to a reduction in the number of the cell transistors and also by a reduction in the number of signal lines.
    • 半导体存储器电路包括以阵列形式布置的多个存储单元,用于读取和写入数据的多条数据线,多条地址线,每条地址线用于传送指定对应的特定存储单元的地址信号;控制单元, 控制数据的读取和写入,用于输入和输出数据的多个数据输入和数据输出端;施加用于允许写入数据的写使能信号的写使能信号输入端;以及至少一个控制 用于清除存储的数据的单元清除信号或用于执行数据的初始化的单元初始化信号的信号输入端子。 通过多条数据线和多条地址线执行数据读取,数据写入和数据清除或数据初始化。 由于单元晶体管的数量的减少以及信号线的数量的减少,要占用的硬件区域减少。
    • 36. 发明授权
    • Time-information obtaining apparatus and radio-controlled timepiece
    • 时间信息获取装置和无线电控制时计
    • US08570839B2
    • 2013-10-29
    • US13297405
    • 2011-11-16
    • Keiichi NomuraHideo Abe
    • Keiichi NomuraHideo Abe
    • G04C11/02G04R20/12
    • G04R20/12G04R20/10
    • A time-information obtaining apparatus is provided with an input waveform data pattern generating unit for sampling a received standard-time radio wave signal to generate an input waveform data pattern, an internal time counting unit for generate a base time, a calculation-waveform data pattern generating unit for generating plural calculation-waveform data patterns based on the base time, an invalid-bit detecting unit for detecting in the plural calculation-waveform data patterns, invalid bits not to be compared with the input waveform data pattern, an error counting unit for comparing the sample values of valid bits of the plural calculation-waveform data patterns with the invalid bits removed and the corresponding sample values of the input waveform data pattern to detect discrepancies between them, and a present-time correcting unit for correcting the base time based on the calculation-waveform data pattern having the smallest number of errors.
    • 时间信息获取装置具有输入波形数据模式产生单元,用于对接收的标准时间无线电波信号进行采样以产生输入波形数据模式,产生基准时间的内部时间计数单元,计算波形数据 模式产生单元,用于基于基准时间产生多个计算波形数据模式;无效比特检测单元,用于在多个计算波形数据模式中检测不与输入波形数据模式比较的无效比特,错误计数 单元,用于将多个计算波形数据模式中的有效位的采样值与去除的无效位相对应,以及相应的输入波形数据模式的采样值以检测它们之间的差异,以及校正基极的当前时间校正单元 基于具有最小错误数的计算波形数据模式的时间。
    • 37. 发明申请
    • APPARATUS AND METHOD FOR SWITCHING A PACKET
    • 用于切换分组的装置和方法
    • US20130077510A1
    • 2013-03-28
    • US13595224
    • 2012-08-27
    • Kazuto NISHIMURAHideo AbeSatoshi Nemoto
    • Kazuto NISHIMURAHideo AbeSatoshi Nemoto
    • H04L12/50H04L12/26
    • G06F11/2005H04L12/6418H04L47/24H04L47/56H04L47/6215H04L49/15H04L49/90
    • An apparatus includes a first switch circuit in an active mode and a second switch circuit in a standby mode. The apparatus receives high-priority packets and low-priority packets. Each switch circuit stores the high-priority packets and the low-priority packets into first and second buffers, respectively. The each switch circuit performs packet-readout processing reading out a packet from the first and second buffers where the packet-readout processing is performed on the first buffer on a priority basis. The apparatus controls the first switch circuit so that a back-pressure time for the high-priority packets becomes longer with increasing amount of data transmitted by the high-priority packets, when a low-priority packet outputted from the first switch circuit is determined to be a packet that has been received at a first time that is later than a second time at which another low-priority packet outputted from the second switch circuit has been received.
    • 一种装置包括处于待机模式的第一开关电路和处于待机模式的第二开关电路。 该设备接收高优先级的报文和低优先级的报文。 每个开关电路分别将高优先级分组和低优先级分组存储到第一和第二缓冲器中。 每个开关电路执行分组读出处理,从第一和第二缓冲器读出分组,其中在第一缓冲器上优先执行分组读出处理。 当从第一开关电路输出的低优先级分组被确定为:第一开关电路时,随着高优先级分组发送的数据量的增加,高优先级分组的背压时间变长, 是在第一时间接收到的分组,该分组晚于在第二时间接收到从第二开关电路输出的另一低优先级分组的分组。
    • 38. 发明授权
    • Radio wave receiver
    • 无线电波接收机
    • US08270922B2
    • 2012-09-18
    • US12777400
    • 2010-05-11
    • Kazuaki AbeHideo Abe
    • Kazuaki AbeHideo Abe
    • H04B1/18
    • H03J3/20H03J7/04H03J2200/06H03J2200/10H04B1/18
    • Disclosed is a radio wave receiver including an antenna to receive a radio wave, a tuning unit to switch a frequency characteristic of the antenna in a stepwise fashion, an oscillation unit to oscillate the antenna and a circuit section of the tuning unit, a receiving process unit to carry out a signal process by extracting a signal of a desired wave among received signals which are received from the antenna, a search control unit in which the oscillation unit is made to generate an oscillation signal at the circuit section and in which the oscillation signal searches a setting condition of the tuning unit which is extracted in the receiving process unit by switching a setting of the tuning unit and a search range deciding unit to selectively decide an adjustable range in which the switching of the setting of the tuning unit is carried out by the search control unit so as to be a specific adjustable range which is a portion of an entire adjustable range of the tuning unit corresponding to a frequency of the desired wave.
    • 公开了一种包括接收无线电波的天线的无线电波接收机,以逐步方式切换天线的频率特性的调谐单元,振荡天线的振荡单元和调谐单元的电路部分,接收处理 单元,通过从从天线接收的接收信号中提取期望波的信号来执行信号处理;搜索控制单元,其中使振荡单元在电路部分产生振荡信号,并且其中振荡 信号通过切换调谐单元和搜索范围决定单元的设置来搜索在接收处理单元中提取的调谐单元的设置条件,以选择性地确定调节单元的设置的切换被传送的可调节范围 由搜索控制单元输出,作为对应的调谐单元的整个可调整范围的一部分的特定可调整范围 到所需波的频率。