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31. 发明授权

US5335203A Semiconductor integrated circuit device with internal voltage drop circuits 失效
标题翻译：具有内部压降电路的半导体集成电路器件
公开(公告)号：US5335203A
公开(公告)日：1994-08-02
申请号：US834354
申请日：1992-02-12
申请人： Kyoko Ishii , Shinichi Miyatake , Tsutomu Takahashi , Shinji Udo , Hiroshi Yoshioka , Mitsuhiro Takano , Makoto Morino
发明人： Kyoko Ishii , Shinichi Miyatake , Tsutomu Takahashi , Shinji Udo , Hiroshi Yoshioka , Mitsuhiro Takano , Makoto Morino
IPC分类号： H01L21/822 , G11C5/14 , G11C7/06 , G11C8/12 , G11C11/401 , G11C11/407 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , G11C11/40 , G11C11/34 , H03K3/01
CPC分类号： G11C5/147 , G11C7/06 , G11C8/12
摘要： A semiconductor memory device has a plurality of divided memory blocks, each of which has its X-system addresses assigned so that an equal number of word lines in a plurality of sets of memory mats and sense amplifiers may be selected. Each memory block is equipped with a plurality of internal voltage drop circuits for generating a supply voltage from the outside into the operating voltages of the sense amplifiers.
摘要翻译：半导体存储器件具有多个划分的存储块，每个存储块的X系统地址被分配，使得可以选择多组存储器堆和读出放大器中相等数量的字线。每个存储块配备有多个内部电压降电路，用于从外部产生电源电压到感测放大器的工作电压。

32. 发明授权

US08773195B2 Semiconductor device having a complementary field effect transistor 有权
标题翻译：具有互补场效应晶体管的半导体器件
公开(公告)号：US08773195B2
公开(公告)日：2014-07-08
申请号：US12662044
申请日：2010-03-29
申请人： Shinichi Miyatake , Seiji Narui , Hitoshi Tanaka
发明人： Shinichi Miyatake , Seiji Narui , Hitoshi Tanaka
IPC分类号： H03K3/01 , G05F3/02
CPC分类号： G05F1/463 , G05F1/462 , G05F3/205 , G05F3/242 , G11C5/147
摘要： A semiconductor device prevents the ON current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a buffer circuit that generates a power-supply voltage of a CMOS; a first replica transistor that is a replica of a p-channel MOS transistor forming the CMOS, and is diode-connected; a second replica transistor that is a replica of an n-channel MOS transistor forming the CMOS, and is diode-connected; and a voltage controller that controls the voltage between the anode and cathode of the replica transistors so that the current value of the current flowing into the replica transistor becomes equal to a given target value. In this semiconductor device, the buffer circuit generates the power-supply voltage, with the target voltage being a voltage that is controlled by the voltage controller.
摘要翻译：半导体器件防止互补场效应晶体管的导通电流随着环境温度的变化而变化。半导体器件包括：产生CMOS的电源电压的缓冲电路; 第一复制晶体管，其是形成CMOS的p沟道MOS晶体管的复制品，并且是二极管连接的; 第二复制晶体管，其是形成CMOS的n沟道MOS晶体管的复制品，并且是二极管连接的; 以及电压控制器，其控制复制晶体管的阳极和阴极之间的电压，使得流入复制晶体管的电流的电流值等于给定的目标值。在该半导体器件中，缓冲电路产生电源电压，目标电压是由电压控制器控制的电压。

33. 发明授权

US08339868B2 Semiconductor device and write control method for semiconductor device 失效
标题翻译：半导体器件的半导体器件和写入控制方法
公开(公告)号：US08339868B2
公开(公告)日：2012-12-25
申请号：US12726703
申请日：2010-03-18
申请人： Shinichi Miyatake
发明人： Shinichi Miyatake
IPC分类号： G11C7/10 , G11C7/06 , G11C7/08 , G11C29/04
CPC分类号： G11C17/18 , G11C11/4091 , G11C29/006 , G11C29/48 , G11C29/785 , G11C2029/2602
摘要： To include a memory cell array that stores therein data in a reversible manner, an antifuse circuit that stores therein data in a nonvolatile manner, a sense amplifier array that temporarily holds data that is read from the memory cell array of data to be written in the memory cell array, and a control circuit that performs a control for writing the data held in the sense amplifier array in the antifuse circuit. According to the present invention, it is not required to provide any dedicated latch circuit for each antifuse element. Therefore, a writing process of writing data in the antifuse circuit can be performed at high speed without causing an increase of the chip dimension due to a dedicated latch circuit.
摘要翻译：为了包括以可逆方式存储数据的存储单元阵列，以非易失性方式存储数据的反熔丝电路，临时保持从要写入的数据的存储单元阵列中读取的数据的读出放大器阵列存储单元阵列，以及控制电路，其执行用于将保持在读出放大器阵列中的数据写入反熔丝电路的控制。根据本发明，不需要为每个反熔丝元件提供任何专用的锁存电路。因此，可以高速执行在反熔丝电路中写入数据的写入处理，而不会导致由于专用锁存电路引起的芯片尺寸的增加。

34. 发明授权

US06538946B2 Semiconductor integrated circuit device 失效
公开(公告)号：US06538946B2
公开(公告)日：2003-03-25
申请号：US09897919
申请日：2001-07-05
申请人： Kouji Arai , Shinichi Miyatake
发明人： Kouji Arai , Shinichi Miyatake
IPC分类号： G11C702
CPC分类号： G11C7/18 , H01L27/10882 , H01L27/10897
摘要： P-type well regions Ap1 and Ap9 on which first and second pre-charge circuits are formed, and p-type well regions Ap2, Ap3, Ap7 and ap8 on which first and second Y-switch circuits are formed, are formed on both ends of a sense amplifier formation region, respectively. A bit line BL2T, which extends from a first memory cell formation region of first and second memory cell formation regions arranged in both sides of the sense amplifier formation region, arrives at a p-type well region An1 on which a sense amplifier is formed, via both a p-type well region Ap1 on which the first pre-charge circuit is formed and p-type well regions Ap2 and Ap3 on which the Y-switch circuit is formed. Therefore, a wiring region c for arranging wirings other than bit lines can be secured on the extended bit line BL2T.

35. 发明授权

US06198128B1 Method of manufacturing a semiconductor device, and semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：US06198128B1
公开(公告)日：2001-03-06
申请号：US09390662
申请日：1999-09-07
申请人： Hisao Asakura , Yoshitaka Tadaki , Toshihiro Sekiguchi , Ryo Nagai , Masafumi Miyamoto , Masayuki Nakamura , Shinichi Miyatake , Tsuyuki Suzuki , Masahiro Hyoma
发明人： Hisao Asakura , Yoshitaka Tadaki , Toshihiro Sekiguchi , Ryo Nagai , Masafumi Miyamoto , Masayuki Nakamura , Shinichi Miyatake , Tsuyuki Suzuki , Masahiro Hyoma
IPC分类号： H01L2972
CPC分类号： H01L29/66537 , H01L21/26586 , H01L21/823814
摘要： In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.
摘要翻译：在用于抑制MISFET的短沟道效应的杂质与其主表面倾斜地引入半导体衬底的情况下，彼此相邻的栅电极被布置成使得沿与栅电极交叉的方向引入的杂质不会被引入位于栅电极之间的半导体衬底的部分中，并且MISFET的源极区域被布置在栅电极之间的部分中。

36. 发明授权

US07952950B2 Semiconductor device including anti-fuse circuit, and method of writing address to anti-fuse circuit 有权
标题翻译：包括反熔丝电路的半导体器件，以及将地址写入反熔丝电路的方法
公开(公告)号：US07952950B2
公开(公告)日：2011-05-31
申请号：US12289196
申请日：2008-10-22
申请人： Shinichi Miyatake , Sumio Ogawa
发明人： Shinichi Miyatake , Sumio Ogawa
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/165 , G11C29/785 , G11C2029/4402
摘要： An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the anti-fuse element. The writing to the latch circuit can be performed in the order of nanoseconds, and thus, even when the defective addresses respectively different are written in a plurality of chips, a writing process to the latch circuit can be completed in a very short period of time. Thereby, an actual process for writing to the anti-fuse element can be performed in parallel for the chips, and as a result, the process for writing to the anti-fuse element can be performed at high speed.
摘要翻译：根据本发明的反熔丝电路包括以非易失性方式保存数据的反熔丝元件和临时保持要写入反熔丝元件的数据的锁存电路。对锁存电路的写入可以以纳秒的量级执行，因此即使当各种不同的不同地址被写入多个芯片时，也可以在非常短的时间内完成对锁存电路的写入处理。由此，可以对于芯片并行地执行写入反熔丝元件的实际处理，结果，可以高速地执行写入反熔丝元件的处理。

37. 发明申请

US20100244908A1 Semiconductor device having a complementary field effect transistor 有权
标题翻译：具有互补场效应晶体管的半导体器件
公开(公告)号：US20100244908A1
公开(公告)日：2010-09-30
申请号：US12662044
申请日：2010-03-29
申请人： Shinichi Miyatake , Seiji Narui , Hitoshi Tanaka
发明人： Shinichi Miyatake , Seiji Narui , Hitoshi Tanaka
IPC分类号： G05F3/16
CPC分类号： G05F1/463 , G05F1/462 , G05F3/205 , G05F3/242 , G11C5/147
摘要： A semiconductor device prevents the ON current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a buffer circuit that generates a power-supply voltage of a CMOS; a first replica transistor that is a replica of a p-channel MOS transistor forming the CMOS, and is diode-connected; a second replica transistor that is a replica of an n-channel MOS transistor forming the CMOS, and is diode-connected; and a voltage controller that controls the voltage between the anode and cathode of the replica transistors so that the current value of the current flowing into the replica transistor becomes equal to a given target value. In this semiconductor device, the buffer circuit generates the power-supply voltage, with the target voltage being a voltage that is controlled by the voltage controller.
摘要翻译：半导体器件防止互补场效应晶体管的导通电流随着环境温度的变化而变化。半导体器件包括：产生CMOS的电源电压的缓冲电路; 第一复制晶体管，其是形成CMOS的p沟道MOS晶体管的复制品，并且是二极管连接的; 第二复制晶体管，其是形成CMOS的n沟道MOS晶体管的复制品，并且是二极管连接的; 以及电压控制器，其控制复制晶体管的阳极和阴极之间的电压，使得流入复制晶体管的电流的电流值等于给定的目标值。在该半导体器件中，缓冲电路产生电源电压，目标电压是由电压控制器控制的电压。

38. 发明申请

US20090109790A1 Semiconductor device including anti-fuse circuit, and method of writing address to anti-fuse circuit 有权
标题翻译：包括反熔丝电路的半导体器件，以及将地址写入反熔丝电路的方法
公开(公告)号：US20090109790A1
公开(公告)日：2009-04-30
申请号：US12289196
申请日：2008-10-22
申请人： Shinichi Miyatake , Sumio Ogawa
发明人： Shinichi Miyatake , Sumio Ogawa
IPC分类号： G11C8/00
CPC分类号： G11C17/18 , G11C17/165 , G11C29/785 , G11C2029/4402
摘要： An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the anti-fuse element. The writing to the latch circuit can be performed in the order of nanoseconds, and thus, even when the defective addresses respectively different are written in a plurality of chips, a writing process to the latch circuit can be completed in a very short period of time. Thereby, an actual process for writing to the anti-fuse element can be performed in parallel for the chips, and as a result, the process for writing to the anti-fuse element can be performed at high speed.
摘要翻译：根据本发明的反熔丝电路包括以非易失性方式保存数据的反熔丝元件和临时保持要写入反熔丝元件的数据的锁存电路。对锁存电路的写入可以以纳秒的量级执行，因此即使当各种不同的不同地址被写入多个芯片时，也可以在非常短的时间内完成对锁存电路的写入处理。由此，可以对于芯片并行地执行写入反熔丝元件的实际处理，结果，可以高速地执行写入反熔丝元件的处理。

39. 发明申请

US20080211058A1 Semiconductor device and method of manufacturing same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080211058A1
公开(公告)日：2008-09-04
申请号：US12007844
申请日：2008-01-16
申请人： Shintaro Asano , Kazutoshi Fukahori , Shinichi Miyatake
发明人： Shintaro Asano , Kazutoshi Fukahori , Shinichi Miyatake
IPC分类号： H01L21/441 , H01L29/86
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises one or more elements subjected to trimming, formed on a main surface side of a silicon substrate and that is/are to be laser trimmed, and an electrode lead of the element subjected to trimming disposed below the position of the element subjected to trimming. The electrode lead subjected to trimming comprises a diffusion layer formed in an uppermost layer of the silicon substrate. The diffusion layer is covered with a protection film made of doped polysilicon and is directly formed on the silicon substrate.
摘要翻译：半导体器件包括经过修整的一个或多个元件，形成在硅衬底的主表面侧并且被激光修整，并且经受修整的元件的电极引线设置在被施加的元件的位置下方修剪经过修整的电极引线包括形成在硅衬底的最上层中的扩散层。扩散层被由掺杂多晶硅制成的保护膜覆盖并直接形成在硅衬底上。

40. 发明授权

US06282141B1 Semiconductor memory device and memory system 有权
标题翻译：半导体存储器件和存储器系统
公开(公告)号：US06282141B1
公开(公告)日：2001-08-28
申请号：US09571512
申请日：2000-05-15
申请人： Masaya Muranaka , Shinichi Miyatake , Yukihide Suzuki , Kanehide Kenmizaki , Makoto Morino , Tetsuya Kitame
发明人： Masaya Muranaka , Shinichi Miyatake , Yukihide Suzuki , Kanehide Kenmizaki , Makoto Morino , Tetsuya Kitame
IPC分类号： G11C800
CPC分类号： G11C7/1069 , G11C7/1006 , G11C7/1051 , G11C11/406 , G11C11/40626 , G11C11/4096
摘要： Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.
摘要翻译：根据特定写入操作模式的指定，同时选择不同存储器阵列中的两个存储器单元，以将写入信号的逻辑1与每个电容器中存在电荷的状态相关联。此外，写入信号的逻辑0与在电容器中不存在电荷以写入相同写入信号的状态相关联。根据特定读取操作模式的指定，同时选择不同存储器阵列中的两个动态存储单元，以将每个动态存储单元的电容器中存在电荷的状态与读取信号的逻辑1和关联响应于写入操作，具有读取信号的逻辑0的电容器中不存在电荷的状态。因此，优先输出两个读取信号的逻辑1。

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