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31. 发明授权

US08135900B2 Integrated memory management and memory management method 有权
标题翻译：集成内存管理和内存管理方法
公开(公告)号：US08135900B2
公开(公告)日：2012-03-13
申请号：US12236880
申请日：2008-09-24
申请人： Atsushi Kunimatsu , Hiroto Nakai , Hiroyuki Sakamoto , Kenichi Maeda
发明人： Atsushi Kunimatsu , Hiroto Nakai , Hiroyuki Sakamoto , Kenichi Maeda
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/0246 , G06F12/0804 , G06F2212/7201 , G06F2212/7211
摘要： An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.
摘要翻译：根据本发明的示例的集成存储器管理装置包括获取单元，其从处理器获取读取的目的地逻辑地址，地址转换单元将读取的目的地逻辑地址转换为非易失性主存储器的读取目的地物理地址，来自非易失性主存储器的访问单元读取与读取的目的地物理地址对应的数据，并且具有等于非易失性主存储器的页面大小的块大小或整数倍的大小，以及传输单元将读取的数据传送到具有取决于非易失性主存储器的页面大小的块大小或整数倍的高速缓存大小的处理器的高速缓存存储器。

32. 发明授权

US5553026A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5553026A
公开(公告)日：1996-09-03
申请号：US364348
申请日：1994-12-27
申请人： Hiroto Nakai , Tadashi Miyakawa , Shigeru Matsuda
发明人： Hiroto Nakai , Tadashi Miyakawa , Shigeru Matsuda
IPC分类号： G11C16/06 , G11C16/02 , G11C16/16 , G11C29/00 , G11C29/12 , G11C29/26 , G11C29/34 , G11C7/00
CPC分类号： G11C29/34 , G11C16/16 , G11C29/26
摘要： The non-volatile memory device comprises a memory cell array, a block decoder, and a decode signal reading section. The memory cell array has a plurality of cell blocks. Each of the cell blocks is composed of a plurality of memory cells arranged roughly into a matrix pattern. Each memory cell has a floating gate to or from which electrons are injected or extracted to write or erase data. The block decoder receives a block address, and outputs a decode signal to select a cell block corresponding to the block address from the cell blocks. The memory cells of the selected block are erased simultaneously. When a control signal is inputted to the block decoder, the block decoder outputs the decode signal to select all the cell blocks for erasure of the memory cells of all the cell blocks simultaneously, irrespective of the block address. The decode signal reading section outputs the decode signal to the outside. The decode signal is applied to the cell blocks and in parallel to the decode signal reading section itself and further outputted to the outside therethrough. In the memory device, the block erase function can be checked at a short time and additionally the other functional blocks can be checked simply.
摘要翻译：非易失性存储器件包括存储单元阵列，块解码器和解码信号读取部分。存储单元阵列具有多个单元块。每个单元块由大致排列成矩阵图案的多个存储单元构成。每个存储单元都有一个浮动栅极，从其中注入或提取电子以写入或擦除数据。块解码器接收块地址，并且输出解码信号以从单元块中选择与块地址相对应的单元块。所选块的存储单元同时被擦除。当控制信号被输入到块解码器时，块解码器输出解码信号以选择用于擦除所有单元块的存储单元的所有单元块，而与块地址无关。解码信号读取部将解码信号输出到外部。解码信号被施加到单元块并且与解码信号读取部分本身并行地进一步输出到外部。在存储器件中，可以在短时间内检查块擦除功能，另外可以简单地检查其他功能块。

33. 发明授权

US5258958A Semiconductor memory device 失效
公开(公告)号：US5258958A
公开(公告)日：1993-11-02
申请号：US778088
申请日：1991-12-12
申请人： Hiroshi Iwahashi , Hiroto Nakai , Kazuhisa Kanazawa , Isao Sato
发明人： Hiroshi Iwahashi , Hiroto Nakai , Kazuhisa Kanazawa , Isao Sato
IPC分类号： G11C7/14 , G11C16/28 , G11C16/32 , G11C29/00 , G11C7/00
CPC分类号： G11C29/842 , G11C16/28 , G11C16/32 , G11C7/14
摘要： There is disclosed a semiconductor memory device comprising memory cells (M11 to Mmn) for storing binary data, and first reference cells (DM11 to DMm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.

34. 发明授权

US5197028A Semiconductor memory device with dual reference elements 失效
标题翻译：具有双参考元件的半导体存储器件
公开(公告)号：US5197028A
公开(公告)日：1993-03-23
申请号：US568034
申请日：1990-08-16
申请人： Hiroto Nakai
发明人： Hiroto Nakai
IPC分类号： G11C17/00 , G11C16/06 , G11C16/28
CPC分类号： G11C16/28
摘要： The invention involves a semiconductor memory device having a memory cell with a drain, a gate and a source. The gate of the memory cell is supplied with a first potential for reading a memory cell data. A first reference line is connected to the drain of a first reference cell to receive a first reference cell data. A second reference cell has a drain, a gate and a source. A second reference line is connected to the drain of the second reference cell for receiving a second reference cell data. A gate voltage generating circuit having an output node is connected to the gate of the first reference cell for controlling the gate potential of the first reference cell so that the potentials at the first and second reference lines have the same power source voltage dependancy. A data detecting circuit reads the memory cell data in accordance with the comparison result between the potentials.
摘要翻译：本发明涉及具有具有漏极，栅极和源极的存储单元的半导体存储器件。存储单元的栅极被提供有用于读取存储单元数据的第一电位。第一参考线连接到第一参考单元的漏极以接收第一参考单元数据。第二参考单元具有漏极，栅极和源极。第二参考线连接到第二参考单元的漏极，用于接收第二参考单元数据。具有输出节点的栅极电压产生电路连接到第一参考单元的栅极，用于控制第一参考单元的栅极电位，使得第一和第二参考线上的电位具有相同的电源电压依赖性。数据检测电路根据电位之间的比较结果读取存储单元数据。

35. 发明授权

US08184470B2 Resistance change memory device and programming method thereof 失效
标题翻译：电阻变化记忆体及其编程方法
公开(公告)号：US08184470B2
公开(公告)日：2012-05-22
申请号：US12668750
申请日：2008-06-25
申请人： Haruki Toda , Hiroto Nakai
发明人： Haruki Toda , Hiroto Nakai
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/31 , G11C2213/32
摘要： A method of programming a resistance change memory device includes: applying program voltage pulses to a memory cell for programming a target resistance value; setting thermal relaxation times between the respective program voltage pulses; and controlling the shape of each the program voltage pulse in accordance with the present cell's resistance value determined by the preceding program voltage pulse application.
摘要翻译：一种对电阻变化存储器件进行编程的方法包括：将程序电压脉冲施加到存储器单元以编程目标电阻值; 设置各个编程电压脉冲之间的热弛豫时间; 并且根据由先前的编程电压脉冲应用确定的当前单元的电阻值来控制每个编程电压脉冲的形状。

36. 发明授权

US08031508B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US08031508B2
公开(公告)日：2011-10-04
申请号：US12266879
申请日：2008-11-07
申请人： Haruki Toda , Hirofumi Inoue , Hiroto Nakai
发明人： Haruki Toda , Hirofumi Inoue , Hiroto Nakai
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C5/063 , G11C8/14 , G11C11/56 , G11C13/0028 , G11C13/004 , G11C2013/0054 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.
摘要翻译：电阻变化存储器件包括：存储单元阵列，其中布置有存储单元，所述存储单元具有用于存储可重写电阻值的可变电阻元件; 由与存储单元阵列中的高电阻状态相同的存储单元形成的参考单元，通过选择并联连接的存储单元的数量来修整参考单元以具有用于检测数据的参考电流值存储单元阵列; 以及读出放大器，被配置为将存储单元阵列中选择的存储单元的单元电流值与参考单元的参考电流值进行比较。

37. 发明授权

US5587948A Nonvolatile semiconductor memory with NAND structure memory arrays 失效
标题翻译：具有NAND结构的非易失性半导体存储器阵列
公开(公告)号：US5587948A
公开(公告)日：1996-12-24
申请号：US490167
申请日：1995-06-14
申请人： Hiroto Nakai
发明人： Hiroto Nakai
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/115 , G11C16/0483
摘要： A memory cell section is divided into a data storage area and a data management information storage area in a column direction. The number of memory cells of each of NAND strings of the data management information storage area is smaller than that of memory cells of each of NAND strings of the data storage area. Word lines are connected in common to NAND strings arranged in the column direction in the data storage area, and two of them extend to be connected in common to the NAND strings arranged in the column direction in the data management information storage area. Bit lines are connected in common to the NAND strings arranged in the row direction.
摘要翻译：存储单元部分被分成列方向的数据存储区和数据管理信息存储区。数据管理信息存储区域的每个NAND串的存储单元的数量小于数据存储区域的每个NAND串的存储单元的数量。字线共同连接在数据存储区域中的列方向上排列的NAND串，并且其中的两个扩展为与数据管理信息存储区域中的列方向上排列的NAND串共同连接。位线被公共连接到沿行方向布置的NAND串。

38. 发明授权

US09367451B2 Storage device management device and method for managing storage device 有权
标题翻译：存储设备管理设备和管理存储设备的方法
公开(公告)号：US09367451B2
公开(公告)日：2016-06-14
申请号：US13491824
申请日：2012-06-08
申请人： Hiroto Nakai , Tatsunori Kanai
发明人： Hiroto Nakai , Tatsunori Kanai
IPC分类号： G06F13/00 , G06F12/06
CPC分类号： G06F12/0638
摘要： According to one embodiment, a storage device management device is connected to a random access memory and a first storage device. When the random access memory includes a free region sufficient to store write data, the write data is stored onto the random access memory. Data on the random access memory selected in the descending order of elapsed time from the last access is sequentially copied onto the first storage device, and a region in the random access memory which has stored the copied data is released. When stored on the random access memory, the read data is read from the random access memory to the processor. When stored on the first storage device, the read data is copied onto the random access memory and read from the random access memory to the processor.
摘要翻译：根据一个实施例，存储设备管理设备连接到随机存取存储器和第一存储设备。当随机存取存储器包括足以存储写入数据的空闲区域时，写入数据被存储到随机存取存储器中。按照从最后访问经过的时间的降序选择的随机存取存储器上的数据被顺序复制到第一存储设备上，并且释放存储了复制数据的随机存取存储器中的区域。当存储在随机存取存储器中时，将读取的数据从随机存取存储器读取到处理器。当存储在第一存储设备上时，将读取的数据复制到随机存取存储器中并从随机存取存储器读取到处理器。

39. 发明申请

US20120124290A1 Integrated Memory Management and Memory Management Method 有权
标题翻译：集成内存管理和内存管理方法
公开(公告)号：US20120124290A1
公开(公告)日：2012-05-17
申请号：US13360903
申请日：2012-01-30
申请人： Atsushi Kunimatsu , Hiroto Nakai , Hiroyuki Sakamoto , Kenichi Maeda
发明人： Atsushi Kunimatsu , Hiroto Nakai , Hiroyuki Sakamoto , Kenichi Maeda
IPC分类号： G06F12/08
CPC分类号： G06F12/0246 , G06F12/0804 , G06F2212/7201 , G06F2212/7211
摘要： An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.
摘要翻译：根据本发明的示例的集成存储器管理装置包括获取单元，其从处理器获取读取的目的地逻辑地址，地址转换单元将读取的目的地逻辑地址转换为非易失性主存储器的读取目的地物理地址，来自非易失性主存储器的访问单元读取与读取的目的地物理地址对应的数据，并且具有等于非易失性主存储器的页面大小的块大小或整数倍的大小，以及传输单元将读取的数据传送到具有取决于非易失性主存储器的页面大小的块大小或整数倍的高速缓存大小的处理器的高速缓存存储器。

40. 发明申请

US20100211725A1 INFORMATION PROCESSING SYSTEM 审中-公开
标题翻译：信息处理系统
公开(公告)号：US20100211725A1
公开(公告)日：2010-08-19
申请号：US12672083
申请日：2008-10-17
申请人： Hiroyuki Nagashima , Hiroto Nakai
发明人： Hiroyuki Nagashima , Hiroto Nakai
IPC分类号： G06F12/00 , G06F12/08 , G11C11/00
CPC分类号： G11C13/0069 , G06F12/0246 , G06F12/0893 , G11C11/005 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C16/3431 , G11C2213/11 , G11C2213/31 , G11C2213/34 , G11C2213/56 , G11C2213/72
摘要： An information processing system comprises a main memory operative to store data, and a control circuit operative to access the main memory for data. The main memory includes a nonvolatile semiconductor memory device containing electrically erasable programmable nonvolatile memory cells each using a variable resistor, and a DRAM arranged as a cache memory between the control circuit and the nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device has a refresh mode of rewriting stored data. The control circuit activates the nonvolatile semiconductor memory device in said refresh mode based on the number of accesses to the nonvolatile semiconductor memory device.
摘要翻译：信息处理系统包括可操作地存储数据的主存储器和可操作以访问主存储器以用于数据的控制电路。主存储器包括：非易失性半导体存储器件，其包含电可擦除的可编程非易失性存储单元，每个可擦除可编程非易失性存储单元使用可变电阻器;以及DRAM，其布置在控制电路和非易失性半导体存储器件非易失性半导体存储器件具有重写存储数据的刷新模式。控制电路基于对非易失性半导体存储器件的访问次数，在所述刷新模式下激活非易失性半导体存储器件。

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