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31. 发明授权

US07611951B2 Method of fabricating MOS transistor having epitaxial region 有权
标题翻译：制造具有外延区域的MOS晶体管的方法
公开(公告)号：US07611951B2
公开(公告)日：2009-11-03
申请号：US11517246
申请日：2006-09-08
申请人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee
发明人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/66636
摘要： Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern. Provided is a method of manufacturing a MOS transistor having an epitaxial region which improves an epitaxial growth rate and which may have fewer defects. The method of manufacturing a MOS transistor having an epitaxial region may include forming a gate pattern on a semiconductor substrate, forming a first ion implantation region having a first damage profile by implanting first impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask, forming a second ion implantation region having a second damage profile adjacent to the first damage profile by implanting second impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask and partially etching a lower portion of sidewalls of the gate pattern and forming in-situ an epitaxial region on the etched semiconductor substrate.
摘要翻译：示例实施例涉及制造半导体器件的方法。其他示例实施例涉及制造具有设置在栅极图案的侧壁的下部中的外延区域的金属氧化物半导体（MOS）晶体管的方法。提供一种制造具有提高外延生长速率并且可能具有较少缺陷的外延区域的MOS晶体管的方法。制造具有外延区域的MOS晶体管的方法可以包括在半导体衬底上形成栅极图案，通过使用栅极图案作为离子注入，将第一杂质离子注入到半导体衬底中，形成具有第一损伤分布的第一离子注入区域通过使用所述栅极图案作为离子注入掩模将所述第二杂质离子注入到所述半导体衬底中，形成具有与所述第一损伤分布相邻的第二损伤分布的第二离子注入区，并部分地蚀刻所述栅极图案的侧壁的下部;以及在蚀刻的半导体衬底上原位形成外延区域。

32. 发明授权

US08338261B2 Semiconductor device including field effect transistor and method of forming the same 有权
标题翻译：包括场效晶体管的半导体器件及其形成方法
公开(公告)号：US08338261B2
公开(公告)日：2012-12-25
申请号：US12851965
申请日：2010-08-06
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.
摘要翻译：半导体器件包括栅极绝缘体和堆叠在衬底上的栅电极，源极/漏极图案填充形成在与栅电极相邻的相对侧的凹陷区域，源极/漏极图案由掺杂有掺杂剂的硅 - 锗构成和设置在源极/漏极图案上的金属锗硅化物层。金属锗硅化物层电连接到源极/漏极图案。此外，与锗源锗排出图案中的锗量和硅量之和的锗量相比，锗量与金锗烷硅化物层中的锗量和硅量之和的比例低。

33. 发明申请

US20080067609A1 Semiconductor Device Including Field Effct Transistor and Method of Forming the Same 有权
标题翻译：包括场效应晶体管的半导体器件及其形成方法
公开(公告)号：US20080067609A1
公开(公告)日：2008-03-20
申请号：US11857157
申请日：2007-09-18
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Ji-Hye Yi
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.
摘要翻译：半导体器件包括栅极绝缘体和堆叠在衬底上的栅电极，源极/漏极图案填充形成在与栅电极相邻的相对侧的凹陷区域，源极/漏极图案由掺杂有掺杂剂的硅 - 锗构成和设置在源极/漏极图案上的金属锗硅化物层。金属锗硅化物层电连接到源极/漏极图案。此外，与锗源锗排出图案中的锗量和硅量之和的锗量相比，锗量与金锗烷硅化物层中的锗量和硅量之和的比例低。

34. 发明申请

US20080006887A1 Semiconductor Devices Including Impurity Doped Region and Methods of Forming the Same 审中-公开
标题翻译：包括杂质掺杂区的半导体器件及其形成方法
公开(公告)号：US20080006887A1
公开(公告)日：2008-01-10
申请号：US11668891
申请日：2007-01-30
申请人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee
发明人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336
CPC分类号： H01L21/26513 , H01L21/26566 , H01L21/2658 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device including an impurity doped region and a method of forming the same. The method includes implanting cluster-shaped dopant ions into a semiconductor substrate to form an impurity implantation region. An annealing process is performed on the impurity implantation region to form an impurity doped region.
摘要翻译：包括杂质掺杂区的半导体器件及其形成方法。该方法包括将簇状掺杂剂离子注入到半导体衬底中以形成杂质注入区。对杂质注入区域进行退火处理以形成杂质掺杂区域。

35. 发明申请

US20120228720A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES HAVING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS 有权
标题翻译：具有不同厚度硅 - 锗层的半导体集成电路器件
公开(公告)号：US20120228720A1
公开(公告)日：2012-09-13
申请号：US13476121
申请日：2012-05-21
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L27/088
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。直接在第一SiGe外延层上形成第二SiGe外延层，以使用不同于第一硅源气体的第二硅源气体来进一步填充源/漏沟槽。

36. 发明申请

US20100006906A1 Semiconductor device, single crystalline silicon wafer, and single crystalline silicon ingot 审中-公开
标题翻译：半导体器件，单晶硅晶片和单晶硅锭
公开(公告)号：US20100006906A1
公开(公告)日：2010-01-14
申请号：US12458500
申请日：2009-07-14
申请人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
发明人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
IPC分类号： H01L29/04
CPC分类号： H01L27/0203 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L29/045 , H01L29/66628
摘要： A semiconductor device includes a single crystalline substrate and an active region defined in the single crystalline substrate, wherein a major axis direction of the active region is aligned with a family direction.
摘要翻译：半导体器件包括单晶衬底和限定在单晶衬底中的有源区，其中有源区的长轴方向与<0,1,1>族方向对齐。

37. 发明申请

US20090170254A1 Method of Manufacturing a Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090170254A1
公开(公告)日：2009-07-02
申请号：US12343134
申请日：2008-12-23
申请人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
发明人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a first stress is formed on the substrate and the first and the second gate electrodes. A mask is formed on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area. The second portion is etched to form a sacrificial spacer on a sidewall of the second gate electrode. The second area of the substrate is partially etched using the mask, the second gate electrode and the sacrificial spacer, to form recesses in the second area of the substrate adjacent the second gate electrode. Patterns having a second stress are formed in the recesses.
摘要翻译：在制造半导体器件的方法中，第一栅电极和第二栅电极形成在衬底的第一区域和第二区域中。在与第一栅电极相邻的衬底的第一区域中形成非结晶区域。在基板和第一和第二栅电极上形成具有第一应力的层。掩模在衬底的第一区域中的该层的第一部分上形成以暴露第二区域中该层的第二部分。蚀刻第二部分以在第二栅电极的侧壁上形成牺牲间隔物。使用掩模，第二栅电极和牺牲隔离物部分蚀刻衬底的第二区域，以在与第二栅电极相邻的衬底的第二区域中形成凹陷。在凹部中形成具有第二应力的图案。

38. 发明申请

US20090258463A1 METHODS OF FABRICATING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS ON SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES FABRICATED THEREBY 有权
标题翻译：在半导体集成电路器件和半导体集成电路器件上制造不同厚度的硅 - 锗层的方法
公开(公告)号：US20090258463A1
公开(公告)日：2009-10-15
申请号：US12419698
申请日：2009-04-07
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/20 , H01L21/768
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。直接在第一SiGe外延层上形成第二SiGe外延层，以使用不同于第一硅源气体的第二硅源气体来进一步填充源/漏沟槽。

39. 发明授权

US07576395B2 Dual gate stack CMOS structure with different dielectrics 有权
标题翻译：具有不同电介质的双栅叠层CMOS结构
公开(公告)号：US07576395B2
公开(公告)日：2009-08-18
申请号：US11044968
申请日：2005-01-27
申请人： Hyung-Suk Jung , Jong-Ho Lee , Hwa-Sung Rhee , Jae-Kwang Choi
发明人： Hyung-Suk Jung , Jong-Ho Lee , Hwa-Sung Rhee , Jae-Kwang Choi
IPC分类号： H01L23/62
CPC分类号： H01L21/823857 , H01L21/28194 , H01L21/3141 , H01L21/31608 , H01L21/31645 , H01L21/823842 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices include a semiconductor substrate having a first doped region and a second doped region having a different doping type than the first doped region. A gate electrode structure on the semiconductor substrate extends between the first and second doped regions and has a gate insulation layer of a first high dielectric constant material in the first doped region and of a second high dielectric constant material, different from the first high dielectric constant material, in the second doped region. A gate electrode is on the gate insulation layer.
摘要翻译：集成电路器件包括具有第一掺杂区域和具有与第一掺杂区域不同的掺杂类型的第二掺杂区域的半导体衬底。半导体衬底上的栅极电极结构在第一和第二掺杂区域之间延伸，并且在第一掺杂区域中具有第一高介电常数材料的栅极绝缘层和不同于第一高介电常数的第二高介电常数材料材料，在第二掺杂区域。栅极电极位于栅极绝缘层上。

40. 发明授权

US08426916B2 Semiconductor integrated circuit devices having different thickness silicon-germanium layers 有权
标题翻译：具有不同厚度的硅 - 锗层的半导体集成电路器件
公开(公告)号：US08426916B2
公开(公告)日：2013-04-23
申请号：US13476121
申请日：2012-05-21
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/36
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。第二SiGe外延层直接形成在第一SiGe外延层上，以使用不同于第一硅源气体的第二硅源气体来进一步填充源极/漏极沟槽。

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