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31. 发明授权

US06366867B2 Method and apparatus for providing controllable compensation factors to a compensated driver circuit which may be used to perform testing of the structural integrity of the compensated driver circuit 有权
标题翻译：为可补偿的驱动器电路提供可控制的补偿因子的方法和装置，其可以用于对经补偿的驱动器电路的结构完整性进行测试
公开(公告)号：US06366867B2
公开(公告)日：2002-04-02
申请号：US09337568
申请日：1999-06-22
申请人： Christopher John Sine , Alper Ilkbahar , Scott W. Murray
发明人： Christopher John Sine , Alper Ilkbahar , Scott W. Murray
IPC分类号： H03K1716
CPC分类号： G01R31/3185 , G01R31/30 , G01R31/31715 , H03K19/018585
摘要： A method and apparatus for providing controllable compensation factors to a compensated driver circuit which may be used to perform testing of the structural integrity of the compensated driver circuit. One disclosed apparatus includes a compensated driver circuit having a number of subcomponents. At least one compensation factor, which may be provided by a compensation circuit, controls which of the subcomponents to enable. An additional circuit is coupled to provide controllable values for the at least one compensation factor.
摘要翻译：一种用于向经补偿的驱动器电路提供可控补偿因子的方法和装置，其可用于对经补偿的驱动器电路的结构完整性进行测试。一种公开的装置包括具有多个子部件的补偿驱动器电路。可以由补偿电路提供的至少一个补偿因子控制哪些子部件能够实现。耦合附加电路以为至少一个补偿因子提供可控制的值。

32. 发明授权

US06288563B1 Slew rate control 有权
标题翻译：压摆率控制
公开(公告)号：US06288563B1
公开(公告)日：2001-09-11
申请号：US09224678
申请日：1998-12-31
申请人： Harry Muljono , Alper Ilkbahar
发明人： Harry Muljono , Alper Ilkbahar
IPC分类号： H03K1716
CPC分类号： H03K19/0005 , H03K19/018585
摘要： Controlling the slew rate of a driver circuit. According to one embodiment of the present invention an output buffer includes a driver circuit having an impedance and a pre-driver circuit to control a slew rate of the driver circuit based on the impedance of the driver circuit.
摘要翻译：控制驱动电路的转换速度。根据本发明的一个实施例，输出缓冲器包括具有阻抗和预驱动器电路的驱动器电路，以根据驱动器电路的阻抗来控制驱动器电路的转换速率。

33. 发明授权

US06172937B2 Multiple synthesizer based timing signal generation scheme 有权
标题翻译：基于多合成器的定时信号生成方案
公开(公告)号：US06172937B2
公开(公告)日：2001-01-09
申请号：US09309049
申请日：1999-05-10
申请人： Alper Ilkbahar , Simon M. Tam , Ian A. Young
发明人： Alper Ilkbahar , Simon M. Tam , Ian A. Young
IPC分类号： G11C800
CPC分类号： G06F1/06
摘要： A multiple synthesizer based timing signal generation scheme is described that allows accurate data and strobe generation in high speed source synchronous system interfaces. Multiple loop locked clock synthesizers (e.g., phase locked loops, delay locked loops) are used to generate multiple clock signals. Data and strobe signals are triggered off of transitions of one of the clock signals. Because multiple loop locked clock synthesizers are used to generate the clock signals, optimal or near optimal alignment of the data and strobe signals can be achieved. Improved alignment of the data and strobe signals provides improved data transmission rates.
摘要翻译：描述了基于多合成器的定时信号生成方案，其允许在高速源同步系统接口中进行准确的数据和频闪生成。多环路锁定时钟合成器（例如，锁相环，延迟锁定环）用于产生多个时钟信号。数据和选通信号从一个时钟信号的转换触发。由于使用多个环路锁定时钟合成器来产生时钟信号，所以可以实现数据和选通信号的最佳或接近最佳对准。改进的数据和选通信号的对准提供了改进的数据传输速率。

34. 发明授权

US08536015B2 Memory cell that includes a carbon-based memory element and methods of forming the same 有权
标题翻译：包含碳基记忆元件的记忆单元及其形成方法
公开(公告)号：US08536015B2
公开(公告)日：2013-09-17
申请号：US13351468
申请日：2012-01-17
申请人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Schricker
发明人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Schricker
IPC分类号： H01L21/00 , H01L21/06 , H01L29/02 , G11C11/00
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/0002 , G11C13/0009 , G11C13/025 , G11C2213/35 , G11C2213/71 , G11C2213/72 , H01L27/1021 , H01L27/285 , H01L51/0048 , Y10S977/712 , Y10S977/72 , Y10S977/721 , Y10S977/723 , Y10S977/734 , Y10S977/788 , Y10S977/789 , Y10S977/79 , Y10S977/855 , Y10S977/943
摘要： In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.
摘要翻译：根据本发明的方面，提供了形成金属 - 绝缘体 - 金属叠层的方法。该方法包括形成第一导电层，在第一导电层上形成电阻率切换碳基材料，并在碳基材料上形成第二导电层，其中碳基材料的厚度不大于十个原子层。还描述了其他方面。

35. 发明授权

US07545689B2 Method and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information 失效
标题翻译：通过保证冗余信息的健康来提高半导体器件产量的方法和装置
公开(公告)号：US07545689B2
公开(公告)日：2009-06-09
申请号：US11894861
申请日：2007-08-21
申请人： Alper Ilkbahar , Derek J. Bosch
发明人： Alper Ilkbahar , Derek J. Bosch
IPC分类号： G11C7/00
CPC分类号： G11C29/76
摘要： A method is provided comprising reading a set of memory cells indicating whether stored redundancy information is reliable and, if the set of memory cells indicates that the stored redundancy information is reliable, determining whether to read primary memory or redundant memory based on the stored redundancy information. Another method is provided comprising reading a set of memory cells associated with a group of memory cells in a primary memory, the set of memory cells indicating whether data can be reliably stored in the group of memory cells; if the set of memory cells indicates that data can be reliably stored in the group of memory cells, storing data in the group of memory cells; and if the set of memory cells does not indicate that data can be reliably stored in the group of memory cells, storing data in a group of memory cells in a redundant memory. In another preferred embodiment, a method for providing memory redundancy is provided.
摘要翻译：提供了一种方法，其包括：读取一组存储器单元，指示存储的冗余信息是否可靠;以及如果存储单元组指示所存储的冗余信息是可靠的，则基于所存储的冗余信息确定是否读取主存储器还是冗余存储器。提供了另一种方法，包括读取与主存储器中的一组存储器单元相关联的一组存储器单元，该组存储器单元指示数据是否可以可靠地存储在存储器单元组中; 如果存储器单元组指示数据可以可靠地存储在存储器单元组中，则将数据存储在存储单元组中; 并且如果存储器单元组不指示数据可以可靠地存储在存储器单元组中，则将数据存储在冗余存储器中的一组存储器单元中。在另一个优选实施例中，提供了一种用于提供存储器冗余的方法。

36. 发明授权

US07233522B2 NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same 有权
标题翻译： NAND存储器阵列结合未选择的存储单元中的沟道区域的电容升压及其操作方法
公开(公告)号：US07233522B2
公开(公告)日：2007-06-19
申请号：US10729831
申请日：2003-12-05
申请人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
发明人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/115 , H01L27/11568 , H01L27/1159
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

37. 发明授权

US07132335B2 Semiconductor device with localized charge storage dielectric and method of making same 有权
标题翻译：具有局部电荷存储电介质的半导体器件及其制造方法
公开(公告)号：US07132335B2
公开(公告)日：2006-11-07
申请号：US10965763
申请日：2004-10-18
申请人： Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker , Luca Fasoli
发明人： Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker , Luca Fasoli
IPC分类号： H01L21/336
CPC分类号： H01L29/66833 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/792
摘要： An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.
摘要翻译：晶体管阵列包括多个晶体管，沿第一方向延伸的多个字线和沿第二方向延伸的多个位线。每个晶体管包括源极，漏极，沟道和局部电荷存储电介质。所述多个晶体管中的第一晶体管和所述多个晶体管中的第二晶体管共用公共源极/漏极。第一晶体管的第一局部电荷存储电介质不与公共源极/漏极重叠，并且第二晶体管的第二局部电荷存储电介质与公共源极/漏极重叠。

38. 发明授权

US06898741B2 Arrangements for self-measurement of I/O timing 失效
标题翻译： I / O时序的自我测量安排
公开(公告)号：US06898741B2
公开(公告)日：2005-05-24
申请号：US10162671
申请日：2002-06-06
申请人： Harry Muljono , Alper Ilkbahar
发明人： Harry Muljono , Alper Ilkbahar
IPC分类号： H03L7/06 , H03L7/081 , G11B5/00 , G06F11/00
CPC分类号： H03L7/0814 , H03L7/06
摘要： Arrangements (circuits, methods, systems) having self-measurement of input/output (I/O) timing.
摘要翻译：具有自测量输入/输出（I / O）时序的布置（电路，方法，系统）。

39. 发明授权

US06737675B2 High density 3D rail stack arrays 有权
标题翻译：高密度3D轨道堆叠阵列
公开(公告)号：US06737675B2
公开(公告)日：2004-05-18
申请号：US10180046
申请日：2002-06-27
申请人： Kedar Patel , Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker
发明人： Kedar Patel , Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker
IPC分类号： H01L2976
CPC分类号： H01L27/088 , H01L27/092 , H01L27/105 , H01L27/1052
摘要： A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.
摘要翻译：半导体器件包括两个晶体管，其中一个晶体管的栅电极和另一个晶体管的源极或漏极位于同一导轨中。单片三维阵列包含多个这样的装置。阵列的不同级别的晶体管优选地具有不同的取向。

40. 发明授权

US06622256B1 System for protecting strobe glitches by separating a strobe signal into pointer path and timing path, filtering glitches from signals on pointer path thereof 失效
标题翻译：用于通过将选通信号分离为指针路径和定时路径来保护频闪毛刺的系统，从其指针路径上的信号滤除毛刺
公开(公告)号：US06622256B1
公开(公告)日：2003-09-16
申请号：US09539666
申请日：2000-03-30
申请人： Sanjay Dabral , Alper Ilkbahar
发明人： Sanjay Dabral , Alper Ilkbahar
IPC分类号： G06F104
CPC分类号： H03K5/1252 , H03K5/133 , H03L7/0805 , H03L7/0995 , H04L7/0008 , H04L7/0025 , H04L7/005
摘要： A method and apparatus for a strobe glitch protection mechanism for a source synchronous I/O link. One method of the present invention comprises separating a transfer clock having a plurality of transfer clock edges into a pointer path and a timing path. Glitches are filtered from signals on said pointer path. The pointer path and the timing path are coupled to generate latch enable signals to latch data bits.
摘要翻译：一种用于源同步I / O链路的选通脉冲干扰保护机制的方法和装置。本发明的一种方法包括将具有多个传送时钟边缘的传送时钟分离成指针路径和定时路径。毛刺从所述指针路径上的信号中滤除。指针路径和定时路径被耦合以产生锁存使能信号以锁存数据位。

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