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    • 32. 发明申请
    • SYNCHRONOUS CLOCK GENERATION APPARATUS AND SYNCHRONOUS CLOCK GENERATION METHOD
    • 同步时钟发生装置和同步时钟生成方法(SYNCHRONOUS CLOCK GENERATION APPARATUS AND SYNCHRONOUS CLOCK GENERATION METHOD
    • US20090304135A1
    • 2009-12-10
    • US12257618
    • 2008-10-24
    • Akihiro SuzukiHiroshi Sonobe
    • Akihiro SuzukiHiroshi Sonobe
    • H04L7/00
    • G06F1/0328H04N5/126
    • A synchronous clock generation apparatus including a multiplier for multiplying a horizontal synchronizing signal by a horizontal synchronizing pulse signal to generate multiplication data, a gain variable digital LPF for extracting only DC components from the multiplication data and capable of performing gain adjustment, and a controller for calculating gain adjustment data, lock center frequency setting data, and LPF gain adjustment data based on the correction data. The controller detects an amount of deviation from the lock center frequency and an amount of variation, displaces the lock center frequency and shifts the lock range along the frequency axis to enlarge the apparent lock range when the amount of deviation is large, and reduces the gain to improve lock precision when the amount of variation is small, without expanding bits in the circuit configuration.
    • 一种同步时钟生成装置,包括:乘法器,用于将水平同步信号乘以水平同步脉冲信号以产生乘法数据;增益可变数字LPF,用于仅从所述乘法数据中提取DC分量并且能够执行增益调整;以及控制器, 基于校正数据计算增益调整数据,锁定中心频率设定数据和LPF增益调整数据。 控制器检测与锁定中心频率的偏差量和变化量,使锁定中心频率移位,并且沿着频率轴移动锁定范围,以在偏差量大时扩大视在锁定范围,并且减小增益 当变化量小时,提高锁定精度,而不会在电路配置中扩展位。
    • 34. 发明授权
    • Data slicer, data slicing method, and amplitude evaluation value setting method
    • 数据切片器,数据切片方法和幅度评估值设定方法
    • US07599003B2
    • 2009-10-06
    • US11500464
    • 2006-08-08
    • Akihiro SuzukiKeiichi Kuzumoto
    • Akihiro SuzukiKeiichi Kuzumoto
    • H04N7/00
    • H04N7/035H04N7/0355H04N7/0357H04N7/0882
    • A data slicer 300 includes a slice level calculation unit 310 that determines whether a detected digital video signal is a CRI signal on the basis of the amplitude of the signal, and sets a reference slice level and upper and lower slice levels which are obtained by providing offset in the reference slice level, by using only the CRI signal; a data slicing unit 160 that binarizes a digital video signal S140 using the slice levels; a decoding circuit 170 that converts binarized serial data into parallel data; and a data selection unit 320 that selects data including no error from the decoded data, and outputs the selected data through a video signal output terminal 190. Therefore, even when the video signal is distorted, this data slicer can set appropriate slice level data to binarize the video signal, thereby suppressing the occurrence rate of decoding errors.
    • 数据限幅器300包括限幅电平计算单元310,其基于信号的幅度来确定检测到的数字视频信号是否为CRI信号,并且设置参考限幅电平和通过提供 通过仅使用CRI信号在参考限幅电平中的偏移; 数据切片单元160,其使用切片级对数字视频信号S140进行二值化; 将二值化的串行数据转换为并行数据的解码电路170; 以及数据选择单元320,其从解码数据中选择不包括错误的数据,并通过视频信号输出端子190输出所选择的数据。因此,即使视频信号失真,该数据限幅器也可以将适当的限幅电平数据设置为 二值化视频信号,从而抑制解码错误的发生率。